Hi Everyone, I'm designing a some FPGA logic to control brushless motor controllers. Along the way, I was wondering if there's a way in Altera Quartus to measure the propagation delay of certain paths in the circuit? Is there a list somewhere in the datasheet that documents the propagation delay per LUT block? I ask because I started generating large blocks with significant critical paths (see image attached), and I started wondering what the limits are between registers. Thanks!
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Just open the static timing analysis (STA) and report the paths you are interested in. In Quartus this tool is called TimeQuest Timing Analyzer, and in case you haven't ever used, there used to be a quite good tutorial provided by Quartus/Altera.
Joshua V. wrote: > I was wondering if there's a way in Altera Quartus to measure the > propagation delay of certain paths in the circuit? Your keyword is "STA": static timing analysis. > Is there a list somewhere in the datasheet that documents the > propagation delay per LUT block? You can find such a figure (its qouted in some hundred ps), but it doesn't help you in any way. 1. you do not know how many LUTs are behind each other for a certain function. 2. lots of the timing is buried in the routing from LUT to LUT. > and I started wondering what the limits are between registers. If the beginning of a logic path is a flipflop and the end of a logic path is a flipflop, then simply set a clock constraint. If the constraint is met, then the logic (and therefore the whole design) is fast enough. And only thats of interest.
Joshua V. wrote: > Along the way, I was wondering if there's a way in Altera Quartus to > measure the propagation delay of certain paths in the circuit? Yes, with TimeQuest Timing Analyzer. For each path, you will get all delay infos of all components. > Is there a list somewhere in the datasheet that documents the > propagation delay per LUT block? I ask because I started generating > large blocks with significant critical paths (see image attached), and I > started wondering what the limits are between registers. Yes, all delays of all components are well documented in the related family datasheet.
Thanks, all! "static timing analysis" was the set of keywords I needed to hunt for. With some quick searching, I was able to find the "max operating frequency" listed after compilation in Quartus.
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