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Forum: FPGA, VHDL & Verilog Error: Coudl not Implement register on this clock edge


von Rex (Guest)


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Hi all,

I want to reset the variable v_count to 0 at the rising-edge of input 
port i_pulse_run. But I get the following errors:

Error: Could not Implement register on this clock edge. and
Error (10821): HDL error at PWM_Gen.vhd(85): can't infer register for 
"CTRL:v_count[15]" because its behavior does not match any supported 
register model.

How else can I reset the variable to 0. I want to reset it only at the 
rising edge of signal i_pulse_run.

Any suggestions are welcomed.
Thanks

1
LIBRARY IEEE;
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USE IEEE.numeric_std.all;
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USE IEEE.std_logic_1164.all;
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..
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..
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..
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CTRL : PROCESS(i_Reset, i_Clock,i_pwm_pulse_run)
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  variable v_PWMout        : std_logic;          
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  variable v_intPWMvalue    : integer range 0 to 8192;  
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  variable  v_updatePWMvalue  : std_logic;          
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  variable v_count : integer range 0 to 65535;
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BEGIN
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IF i_Reset = '0' THEN
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    -- Asynchronous reset
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    o_PWM        <= '0';
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    s_PWMCounter     <= 0;
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    v_updatePWMvalue  := '0';
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  ELSIF rising_edge(i_Clock) THEN
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    -- Increment the PWM counter
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    IF s_PWMCounter < i_PWM_Freq_Div - 1 THEN
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      s_PWMCounter   <= s_PWMCounter + 1;
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    ELSE
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      s_PWMCounter   <= 0;
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      if rising_edge(i_pulse_run) then
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      v_count := 0; -- Error 
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      end if;
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      if i_pwm_pulse_en = '1' AND  v_count < i_pulse_count +1 THEN
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         v_count := v_count + 1;
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      END IF;
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    END IF;
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..
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..
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END IF;
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END PROCESS CTRL;

von Lothar M. (lkmiller) (Moderator)


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Rex wrote:
> ELSIF rising_edge(i_Clock) THEN
>   ....
>       if rising_edge(i_pulse_run) then
In what hardware may have two different signals a rising edge at the 
very same time?
And what kind of hardware device may be able to be triggered on two 
clocks?
I don't know any. At least not insid any FPGA nowadays...

> I want to reset the variable v_count to 0 at the rising-edge of input
> port i_pulse_run.
Then you must sync in this asynchronous signal and implement a 
edge-detection:
1
-- shift register for edge-detection
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signal sr_pulse_run : std_logic_vector(1 downto 0) := "00";
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:
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:
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-- sync in the "run pulse" with a shift register
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sr_pulse_run <= sr_pulse_run(0) & i_pulse_run when rising_edge(i_Clock);
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:
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:
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IF i_Reset = '0' THEN       ----<<<< That is usually not neccessary!
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    -- Asynchronous reset
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    o_PWM        <= '0';
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    s_PWMCounter     <= 0;
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    v_updatePWMvalue  := '0';
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  ELSIF rising_edge(i_Clock) THEN
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    -- Increment the PWM counter
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    IF s_PWMCounter < i_PWM_Freq_Div - 1 THEN
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      s_PWMCounter   <= s_PWMCounter + 1;
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    ELSE
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      s_PWMCounter   <= 0;
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      if sr_pulse_run="01" then     ---- rising edge on signal
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      v_count := 0; -- Error 
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      end if;
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      if i_pwm_pulse_en = '1' AND  v_count < i_pulse_count +1 THEN
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         v_count := v_count + 1;
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      END IF;
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    END IF;



And tell me: why the heck do you use so many variables? Did you program 
processors in the last time?

: Edited by Moderator

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