Rex wrote:
> ELSIF rising_edge(i_Clock) THEN
> ....
> if rising_edge(i_pulse_run) then
In what hardware may have two different signals a rising edge at the
very same time?
And what kind of hardware device may be able to be triggered on two
clocks?
I don't know any. At least not insid any FPGA nowadays...
> I want to reset the variable v_count to 0 at the rising-edge of input
> port i_pulse_run.
Then you must sync in this asynchronous signal and implement a
edge-detection:
1 | -- shift register for edge-detection
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2 | signal sr_pulse_run : std_logic_vector(1 downto 0) := "00";
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3 | :
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4 | :
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5 | -- sync in the "run pulse" with a shift register
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6 | sr_pulse_run <= sr_pulse_run(0) & i_pulse_run when rising_edge(i_Clock);
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7 | :
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8 | :
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9 | IF i_Reset = '0' THEN ----<<<< That is usually not neccessary!
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10 | -- Asynchronous reset
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11 | o_PWM <= '0';
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12 | s_PWMCounter <= 0;
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13 | v_updatePWMvalue := '0';
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14 | ELSIF rising_edge(i_Clock) THEN
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15 | -- Increment the PWM counter
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16 |
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17 | IF s_PWMCounter < i_PWM_Freq_Div - 1 THEN
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18 | s_PWMCounter <= s_PWMCounter + 1;
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19 | ELSE
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20 | s_PWMCounter <= 0;
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21 | if sr_pulse_run="01" then ---- rising edge on signal
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22 | v_count := 0; -- Error
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23 | end if;
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24 | if i_pwm_pulse_en = '1' AND v_count < i_pulse_count +1 THEN
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25 | v_count := v_count + 1;
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26 | END IF;
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27 | END IF;
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And tell me: why the heck do you use so many variables? Did you program
processors in the last time?