Hi all, I want to reset the variable v_count to 0 at the rising-edge of input port i_pulse_run. But I get the following errors: Error: Could not Implement register on this clock edge. and Error (10821): HDL error at PWM_Gen.vhd(85): can't infer register for "CTRL:v_count[15]" because its behavior does not match any supported register model. How else can I reset the variable to 0. I want to reset it only at the rising edge of signal i_pulse_run. Any suggestions are welcomed. Thanks
1 | LIBRARY IEEE; |
2 | USE IEEE.numeric_std.all; |
3 | USE IEEE.std_logic_1164.all; |
4 | ..
|
5 | ..
|
6 | ..
|
7 | CTRL : PROCESS(i_Reset, i_Clock,i_pwm_pulse_run) |
8 | |
9 | variable v_PWMout : std_logic; |
10 | variable v_intPWMvalue : integer range 0 to 8192; |
11 | variable v_updatePWMvalue : std_logic; |
12 | variable v_count : integer range 0 to 65535; |
13 | |
14 | BEGIN
|
15 | IF i_Reset = '0' THEN |
16 | -- Asynchronous reset
|
17 | o_PWM <= '0'; |
18 | s_PWMCounter <= 0; |
19 | v_updatePWMvalue := '0'; |
20 | ELSIF rising_edge(i_Clock) THEN |
21 | -- Increment the PWM counter
|
22 | |
23 | IF s_PWMCounter < i_PWM_Freq_Div - 1 THEN |
24 | s_PWMCounter <= s_PWMCounter + 1; |
25 | ELSE
|
26 | s_PWMCounter <= 0; |
27 | if rising_edge(i_pulse_run) then |
28 | v_count := 0; -- Error |
29 | end if; |
30 | if i_pwm_pulse_en = '1' AND v_count < i_pulse_count +1 THEN |
31 | v_count := v_count + 1; |
32 | END IF; |
33 | END IF; |
34 | |
35 | ..
|
36 | ..
|
37 | END IF; |
38 | END PROCESS CTRL; |
Rex wrote: > ELSIF rising_edge(i_Clock) THEN > .... > if rising_edge(i_pulse_run) then In what hardware may have two different signals a rising edge at the very same time? And what kind of hardware device may be able to be triggered on two clocks? I don't know any. At least not insid any FPGA nowadays... > I want to reset the variable v_count to 0 at the rising-edge of input > port i_pulse_run. Then you must sync in this asynchronous signal and implement a edge-detection:
1 | -- shift register for edge-detection
|
2 | signal sr_pulse_run : std_logic_vector(1 downto 0) := "00"; |
3 | :
|
4 | :
|
5 | -- sync in the "run pulse" with a shift register
|
6 | sr_pulse_run <= sr_pulse_run(0) & i_pulse_run when rising_edge(i_Clock); |
7 | :
|
8 | :
|
9 | IF i_Reset = '0' THEN ----<<<< That is usually not neccessary! |
10 | -- Asynchronous reset
|
11 | o_PWM <= '0'; |
12 | s_PWMCounter <= 0; |
13 | v_updatePWMvalue := '0'; |
14 | ELSIF rising_edge(i_Clock) THEN |
15 | -- Increment the PWM counter
|
16 | |
17 | IF s_PWMCounter < i_PWM_Freq_Div - 1 THEN |
18 | s_PWMCounter <= s_PWMCounter + 1; |
19 | ELSE
|
20 | s_PWMCounter <= 0; |
21 | if sr_pulse_run="01" then ---- rising edge on signal |
22 | v_count := 0; -- Error |
23 | end if; |
24 | if i_pwm_pulse_en = '1' AND v_count < i_pulse_count +1 THEN |
25 | v_count := v_count + 1; |
26 | END IF; |
27 | END IF; |
And tell me: why the heck do you use so many variables? Did you program processors in the last time?
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Edited by Moderator
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