puka1012 wrote:
> the spi slave implementation from open cores.org
I had finished reading the code after those 2 lines:
1 | use ieee.numeric_std.all;
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2 | use ieee.std_logic_unsigned.all;
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Its obviously a beginners code. That can be easily seen throughout the
code at such things:
- a "double-clocked" process
- the sensitivity list has too much signals in it
1 | in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is -- clk_i is enough here!
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2 | begin
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3 | if clk_i'event and clk_i = '1' then -- a clock!
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4 | ...
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5 | end if;
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6 |
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7 | if clk_i'event and clk_i = '1' then -- and once more a clock? :-o
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8 | ...
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9 | end if;
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10 | end process in_transfer_proc;
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And this: a clocked process which has also a async part. Wow!
1 | out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg,
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2 | do_valid_A, do_valid_B, do_valid_D,
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3 | di_req_o_A, di_req_o_B, di_req_o_D) is
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4 | begin
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5 | -- CLOCKED !!!
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6 | if clk_i'event and clk_i = '1' then
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7 | ....
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8 | end if;
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9 |
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10 | -- COMBINATORIAL !!!
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11 | do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
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12 | di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
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13 | end process out_transfer_proc;
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Its easy to implement a thoroughly synchronous(!!) SPI slave interface
in less then 100 lines of code. See the
Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?" (try google
translator)...