Hello, can anyone tell me how I can use the UART-Interface on my Lattice ICEStick? I want to send and receive Data via this interface, unfortunately I am not able to find any tutorials or other information for my lattice device. Thank you for your support. Sincerely, Banane
Banane wrote: > can anyone tell me how I can use the UART-Interface on my Lattice > ICEStick? What about using Googles? https://www.google.de/search?q=iCEstick+uart https://github.com/cyrozap/iCEstick-UART-Demo http://www.element14.com/community/docs/DOC-55683/l/lattice-semiconductor-ice40hx1k-stick-evn-icestick-evaluation-kit
Lothar M. wrote: > Banane wrote: >> can anyone tell me how I can use the UART-Interface on my Lattice >> ICEStick? > What about using Googles? > https://www.google.de/search?q=iCEstick+uart > https://github.com/cyrozap/iCEstick-UART-Demo > http://www.element14.com/community/docs/DOC-55683/... Thank you for your response. I've tried to synthesize the verilog file from the demo, but every time I am getting this error: evhw2@evhw2:~/Desktop/icestorm/iCEstick-UART-Demo$ make flash yosys -p "read_verilog uart_demo.v; synth_ice40 -flatten -blif uart_demo.blif" /----------------------------------------------------------------------- -----\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2015 Clifford Wolf <clifford@clifford.at> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------- -----/ Yosys 0.5+287 (git sha1 09b51cb, clang 3.4-1ubuntu3 -fPIC -Os) -- Running command `read_verilog uart_demo.v; synth_ice40 -flatten -blif uart_demo.blif' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `uart_demo.v' to AST representation. Generating RTLIL representation for module `\uart'. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing SYNTH_ICE40 pass. 2.1. Executing Verilog-2005 frontend. Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Successfully finished Verilog frontend. 2.2. Executing HIERARCHY pass (managing design hierarchy). 2.2.1. Finding top of design hierarchy.. root of 1 design levels: top root of 0 design levels: uart Automatically selected top as design top module. 2.2.2. Analyzing design hierarchy.. Top module: \top Used module: \uart 2.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\uart'. ERROR: Requested parameter `\sys_clk_freq' does not exist in module `\uart'! make: *** [uart_demo.blif] Error 1 evhw2@evhw2:~/Desktop/icestorm/iCEstick-UART-Demo$ sudo make flash [sudo] password for evhw2: yosys -p "read_verilog uart_demo.v; synth_ice40 -flatten -blif uart_demo.blif"
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Edited by Moderator
Banane wrote: > but every time I am getting this error: So, now you must start thinking. It seems a good time for that... > Requested parameter `\sys_clk_freq' does not exist in module `\uart'! What is that parameter "sys_clk_freq" in module "uart"? How could it be passed to that module? Is a kind of "global define" for "sys_clk_freq" missing?
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