Forum: FPGA, VHDL & Verilog Vector with several components

von jackoup (Guest)

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I am trying to realize a dot product in VHDL between two vectors : a and 

A and b will both be composed of 8 values (a1, a2 ... a8) and each of 
those values will be a 8 bits integer.

How can i declare this on vhdl ? Is it possible to have only 2 entrees 
(a and b) or should i declare 2*8 entrees for all the vectors components 

Thanks a lot,

von Chris (Guest)

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type yourarray is array(7 downto 0) of std_logic_vector(7 downto 0);


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