I'm making my first steps in PlanAhead v14.7. When configuring my Nexys
2 board with the bitstream generated from my PA project in IMPACT, I
receive a warning about CCLK being used as the startup clock and that
JtagClock is needed, because the device is going to be configured with
JTAG. IMPACT patches the bitstream file in memory eventually to fix it
and loads it into the device.
This does not work in Adept however, which complains that it will not
work with CCLK.
I know how to set the startup clock ISE, but I have now idea how to
specify the startup clock in PlanAhead. Anybody?