Forum: FPGA, VHDL & Verilog Multiplexer Help

von john Wilson (Guest)

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Im trying to implement a generic Mux on the spartan 3e using Xilinx ISE.
I am having issues with this,
I have an input, call it INPUT_A that can be Q bits wide and a select, 
SEL_B that is R bits wide. output is 3 bits
In the entity its like this:
generic R=2, Q=3
INPUT_A is a std_logic_vector (2**R)*Q downto 0);
SEL_B std_logic_vector (R-1 down to 0);
output std_logic_vector(Q downto 0);

I have the entity OK, but just cant get the device itself.
i have something like this for the actual device in one line:
output<INPUT_A((conv_integer(SEL_B)+1)*Q-1 downto conv_integer(SEL_B)*Q)

Can anyone give any ideas on this?
Thank you

von P. K. (pek)

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john Wilson wrote:
> output<INPUT_A((conv_integer(SEL_B)+1)*Q-1 downto conv_integer(SEL_B)*Q)

What is exatly your problem? This does not look so bad. Use correct 
assignments and type castings. The following line works perfectly for me 
(and may suit as  a starting point to you):
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;


OutxD <= InxDI(10*pNr+ 9 downto 10*pNr);

where pNr is an integer, range limited to InxDI, all others are of type 

: Edited by User
von Lothar M. (lkmiller) (Moderator)

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P. K. wrote:
> Use correct assignments and type castings.
And pls. do not use those use IEEE.STD_LOGIC_ARITH and 
IEEE.STD_LOGIC_UNSIGNED from the last millenium.

Use the numeric_std instead. It is straightforward and simple. Try that 
with Google translator (its German):

: Edited by Moderator
von John Wilson (Guest)

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Hi guys,
thanks for your replies.
Ive begun writing a test bench to test this.
Just a standard testbench without any error outputs to check the 
waveform when I simulate.
I'm having trouble trying to implement a testbench however.
I'm thinking I need two loops to test all possible inputs as the output 
relies on select?
any ideas on how to generic testbench this?
thanks guys

von John Wilson (Guest)

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I wanted to know if anyone had some experience designing a testbench, 
for a generic multiplexer.

Select is M

the input is generic N

Im more concerned with the loop to make the testbench UUT go through all 
the possible combinations to confirm the correct otuputs?

any help guys


von Lothar M. (lkmiller) (Moderator)

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John Wilson wrote:
> Select is M
> the input is generic N
How do they relate to each other?
Show the code or at least the port definition of that multiplexer. There 
must be at least 3 signals to see: input(s), select and output

And pls: do not start every other day an new thread for the very same 
question! I concatenated them as they relate the same topic...

: Edited by Moderator
von John Wilson (Guest)

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Hi Lothar,
Thanks for the reply,
The code for the implementation is below, the synthesizer gives a 
warning for the implementation but its not the main issues. Its just im 
not sure how to do the testbench for a generic mux?
entity MUX is
        M: INTEGER := 2);

    Port ( myin : in  STD_LOGIC_VECTOR((2**M)*N-1 downto 0);
           myout : out  STD_LOGIC_VECTOR(N-1 downto 0);
           sel : in  STD_LOGIC_VECTOR (M-1 downto 0));
end MUX;

architecture Behavioral of MUX is
--variable intnewsel:= conv_integer(sel);
myout<=myin((conv_integer(sel)+1)*N-1 downto conv_integer(sel)*N);
--end process;
end Behavioral;

    -- Component Declaration for the Unit Under Test (UUT)
         myin : IN  std_logic_vector((2**M)*N-1 downto 0);
         myout : OUT  std_logic_vector(N-1 downto 0);
         sel : IN  std_logic_vector(M-1 downto 0)

   signal TX_in : std_logic_vector((2**M)*N-1 downto 0) := (others => '0');
   signal TX_sel : std_logic_vector(M-1 downto 0) := (others => '0');

   signal TX_out : std_logic_vector(N-1 downto 0);


  -- Instantiate the Unit Under Test (UUT)
   uut: MUX PORT MAP (
          myin => TX_in,
          myout => TX_out,
          sel => TX_sel

   -- Clock process definitions

   -- Stimulus process
   MUX_UUT: process
  variable vmyout:std_logic_vector (N-1 downto 0);
   for i in 0 to 2**M LOOP
    vmyout := Tx_in(i);
    wait for 100 ns;  

End Loop;   
    -- hold reset state for 100 ns.

      -- insert stimulus here 

   end process;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)

Attached files:

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And the manual for the editbox here ist just a few lines above:
Rules — please read before posting
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    [vhdl]VHDL code[/vhdl]

John Wilson wrote:
> The code for the implementation is below ...
> entity MUX is
Did you know: each VHDL code sarts well before the keyword "entity".
All of mine start with "library"...

> conv_integer
A lttle reminder: https://embdev.net/topic/377905?goto=4300680#4292803

> myout <= vmyout;
You cannot assign a value to an output. Have a closer look to the 
signals direction, it was you giving them that names...

> variable vmyout:std_logic_vector (N-1 downto 0);
> vmyout := Tx_in(i);
> myout <= vmyout;
A little poking around in the dark?
1. You do not need a variable here...
2. Why do you read a value from a port, where you should hand over a 
input value, and write it to a port, where an output is assigned by 
the UUT?

To keep things subtantially short: have a very close look at my 

: Edited by Moderator
von John Wilson (Guest)

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Hi Lothar,
Thank you very much for your help, I really appreciate it.
I was as you rightly guessed poking in the dark  in some places.
Ive looked over your code and it makes a lot of sense.
i did try running  a simulation, it passes the behavioral check without 
issues, the muxout however doesn't generate the result you got from your 
thank you

von Lothar M. (lkmiller) (Moderator)

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John Wilson wrote:
> the muxout however doesn't generate the result you got from your
> simulation.
What instead?
Did you use exactly my code?
Can you show a screenshot of your simulations waveform?
What simulator did you use? (Mine was ISIM from ISE14.2)

von Rukhsana (Guest)

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Oi murilo, em geral he1 2  cinomhas  pra seguir na busca por reduzir o 
espae7o ocupado pelo cf3digo no FPGA:1) Regular as configurae7f5es da 
tua ferramenta de sedntese (ISE, Quartus, etc). Vocea pode tentar 
aumentar o nedvel de otimizae7e3o pra espae7o (vai aumentar bastante seu 
tempo de sedntese), pode tentar mudar a codificae7e3o das suas me1quinas 
de estados (usar menos bits), ou ente3o pode tentar colocar o 
armazenamento em BRAMs ao inve9s de em flip-flops (tem uma 
configurae7e3o no ISE pra isso, mas eu ne3o me lembro onde).2) Diminuir 
o paralelismo no seu design: Essa alternativa je1 e9 mais difedcil, mas 
vai resultar numa mudane7a maior no espae7o ocupado no FPGA. O objetivo 
e9 vocea tentar localizar blocos no seu cf3digo VHDL em que operae7f5es 
se3o feitas em paralelo, ou seja, em que he1 replicae7e3o de hardware. 
Daed vocea deve tentar serializar essas operae7f5es, usando por exemplo 
uma me1quina de estados para controlar a sequeancia.  No exemplo do 
somador do post, a gente poderia ter usado apenas UM FULL-ADDER de 1 
bit, ao inve9s de N. Isso iria diminuir o espae7o ocupado na FPGA.Espero 
ter te ajudado um pouco, e ne3o confundido mais :)


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