Hi guys,
thanks for your replies.
Ive begun writing a test bench to test this.
Just a standard testbench without any error outputs to check the 
waveform when I simulate.
I'm having trouble trying to implement a testbench however.
I'm thinking I need two loops to test all possible inputs as the output 
relies on select?
any ideas on how to generic testbench this?
thanks guys

Hi,

I wanted to know if anyone had some experience designing a testbench, 
for a generic multiplexer.

Select is M

the input is generic N

Im more concerned with the loop to make the testbench UUT go through all 
the possible combinations to confirm the correct otuputs?

any help guys

thanks

Hi Lothar,
Thanks for the reply,
The code for the implementation is below, the synthesizer gives a 
warning for the implementation but its not the main issues. Its just im 
not sure how to do the testbench for a generic mux?

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entity MUX is

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GENERIC(N: INTEGER := 3;

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        M: INTEGER := 2);

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    Port ( myin : in  STD_LOGIC_VECTOR((2**M)*N-1 downto 0);

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           myout : out  STD_LOGIC_VECTOR(N-1 downto 0);

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           sel : in  STD_LOGIC_VECTOR (M-1 downto 0));

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end MUX;

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architecture Behavioral of MUX is

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begin

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--mux_proc:process(myin,sel)

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--variable intnewsel:= conv_integer(sel);

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--begin

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myout<=myin((conv_integer(sel)+1)*N-1 downto conv_integer(sel)*N);

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--end process;

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end Behavioral;

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ENTITY GENERIC_MUX_UUT IS

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END GENERIC_MUX_UUT;

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ARCHITECTURE behavior OF GENERIC_MUX_UUT IS 

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    -- Component Declaration for the Unit Under Test (UUT)

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    COMPONENT MUX

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    PORT(

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         myin : IN  std_logic_vector((2**M)*N-1 downto 0);

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         myout : OUT  std_logic_vector(N-1 downto 0);

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         sel : IN  std_logic_vector(M-1 downto 0)

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        );

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    END COMPONENT;

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   --Inputs

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   signal TX_in : std_logic_vector((2**M)*N-1 downto 0) := (others => '0');

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   signal TX_sel : std_logic_vector(M-1 downto 0) := (others => '0');

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   --Outputs

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   signal TX_out : std_logic_vector(N-1 downto 0);

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BEGIN

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  -- Instantiate the Unit Under Test (UUT)

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   uut: MUX PORT MAP (

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          myin => TX_in,

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          myout => TX_out,

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          sel => TX_sel

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        );

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   -- Clock process definitions

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   -- Stimulus process

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   MUX_UUT: process

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  variable vmyout:std_logic_vector (N-1 downto 0);

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   begin    

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   for i in 0 to 2**M LOOP

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    vmyout := Tx_in(i);

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    wait for 100 ns;  

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End Loop;   

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    -- hold reset state for 100 ns.

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      -- insert stimulus here 

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      wait;

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   end process;

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myout<=vmyout;

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END;

Hi Lothar,
Thank you very much for your help, I really appreciate it.
I was as you rightly guessed poking in the dark  in some places.
Ive looked over your code and it makes a lot of sense.
i did try running  a simulation, it passes the behavioral check without 
issues, the muxout however doesn't generate the result you got from your 
simulation.
thank you

Oi murilo, em geral he1 2  cinomhas  pra seguir na busca por reduzir o 
espae7o ocupado pelo cf3digo no FPGA:1) Regular as configurae7f5es da 
tua ferramenta de sedntese (ISE, Quartus, etc). Vocea pode tentar 
aumentar o nedvel de otimizae7e3o pra espae7o (vai aumentar bastante seu 
tempo de sedntese), pode tentar mudar a codificae7e3o das suas me1quinas 
de estados (usar menos bits), ou ente3o pode tentar colocar o 
armazenamento em BRAMs ao inve9s de em flip-flops (tem uma 
configurae7e3o no ISE pra isso, mas eu ne3o me lembro onde).2) Diminuir 
o paralelismo no seu design: Essa alternativa je1 e9 mais difedcil, mas 
vai resultar numa mudane7a maior no espae7o ocupado no FPGA. O objetivo 
e9 vocea tentar localizar blocos no seu cf3digo VHDL em que operae7f5es 
se3o feitas em paralelo, ou seja, em que he1 replicae7e3o de hardware. 
Daed vocea deve tentar serializar essas operae7f5es, usando por exemplo 
uma me1quina de estados para controlar a sequeancia.  No exemplo do 
somador do post, a gente poderia ter usado apenas UM FULL-ADDER de 1 
bit, ao inve9s de N. Isso iria diminuir o espae7o ocupado na FPGA.Espero 
ter te ajudado um pouco, e ne3o confundido mais :)