my Verilpg code:
module top (input a, b, output D1);
reg a = 1;
reg b = 1;
assign y = a & b;
if (y == 1)
assign D1 = 1;
To explain this: I want to see, if y = 1 or true (it should get true/1
because a and b are 1 so the logic tile sends an 1) the LED should
light. But I' bad in programing Verilog so please just help me learning.
Maybe the y need to be an in/output? All help is welcome.
I'm working with icestorm tools and can't even generate the .blif file.
ERROR: Condition for generate if at program1.v:10 is not constant!
Thanks for help.