Hello,

my Verilpg code:

module top (input a, b, output D1);

 reg a = 1;
 reg b = 1;

integer y;

assign y = a & b;

if (y == 1)

assign D1 = 1;

else

;

endmodule

To explain this: I want to see, if y = 1 or true (it should get true/1 
because a and b are 1 so the logic tile sends an 1) the LED should 
light. But I' bad in programing Verilog so please just help me learning.
Maybe the y need to be an in/output? All help is welcome.

I'm working with icestorm tools and can't even generate the .blif file.
Error:
ERROR: Condition for generate if at program1.v:10 is not constant!

Thanks for help.

Verilog wrote:
> assign D1 = 1;

I have no idea how the verilog syntax works, but it seems curious that 
you assign an integer. It should probably be something like "1'b1"

And by the way, you're having a weird coding style.
What you want to write is one line. If you are writing more you're doing 
wrong. I would guess:
assign D1 = a & b

I also doubt you can assign a value to an input. Especially an integer.