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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
SPI slave open core simulation diagram puka1012 3
Synthesizer Problems Hugh Smith 2
FPGA for Evolvable Hardware Implementation Dude 7
Data generation for CRC-16 CCITT Hatim B. 0
Example of using Dual Port Ram (Lattice MachXO2)? Kenny Millar 1
Reversing bits puka1012 13
Quadrature decoder Chris 23
SPI read and write registers (32 bit data) puka1012 2
X-Ray tube Current Control based on PWM Alex 0
Digilent Ambient Light Sensor not working YS Park 0
need help with writing verilog code troy 1
locked VHDL code for EROSION of a image krish sharma 7
Read/Write EPCS64 flash from Nios II jeorges FrenchRivera 2
Control tube heating based on PWM Values Alex 2
ERROR instantiating module Hugh Smith 4
Mixed Design Shenji Kagawa 1
Netlist theoretical doubt Junior Hpc 1
Instantiating IOBUF in MHS file MarkusMSchmidt 0
From netlist to VHDL Junior Hpc 3
Recommendations on big and small FPGA boards? Timothy Miller 3
to find error in vhdl code Anchal Agarwal 7
Using EPCS64 Device with DE0 nano Board jeorges FrenchRivera 0
From java to FPGA (general concept) Junior Hpc 3
Spi,Quadrature encoder combined?Insight Please Chris 3
nested ifs vs elsif SparkyT 2
Puzzle- Position of Most Signi '1' in an N-bit register Antony Mathew 8
mux in verilog lkb 3
Multi-width RAM access? Warren Toomey 1
SysGen, Parallelization Liam Smith 0
8-bit avr microcontroller counter verilog code Sina Jack 6
Ethernet MAC - PHY transmit Szymon Piotrowski 14
Socket Communication with FPGAs Anny Lin 3
the FMITE processor Hugh Aguilar 2
locked Emergency I need your help Lily La 6
Controlling a led matrix Moi Fener 7
SPI slave in FPGA SparkyT 3
Using C programming to call VHDL implementation John Porter 4
put attributes into file possible? spyro 1
vhdl decoder, preventing previous position output duplication Christopher 9
Newbie question on FPGA Sreedev Krishnakumar 1
Using VHDL Arithmetic Operators on FPGA Chips Warren Toomey 3
implement Filter Bahare Moradi 12
BPI(byte peripheral interface) Micron StrataFlash Memory NOR Flash Interface Arun Alex Emmanuel 0
help with choosing FPGA board Lukas 1
Using Special characters in Module name Anil 0
Describe in VHDL a generator parallel 4 bits to serial 1 bit issam sassi 1
describe delay on Verilog NSergeevich 0
Choosing the right FPGA board FrewCen 3
How to generate random delay in "generate" loop? RandomDelay 2
M9K memory block issue in Cyclone IV jeorges FrenchRivera 12
VHDL : 4-Bit Adder and Subtractor Problem Mahmood Mehri 1