# Forum: FPGA, VHDL & Verilog 2's Complement in verilog

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How do I convert inputs into  two complement and perform alu operation
on those input to produce a o/p which should also be in two's
complement?

The question which I came across is

A module has three inputs: two 32-bit signed numbers represented in 2'c
complement format (A & B) and a 2-bit control (CTRL).  It produces four
outputs: a 32-bit result (R),  an overflow flag (O), a sign flag (N),
and a Zero flag (Z).  The result should be in 2's complement format as
well.

I am struck in 2'c complement part. any ideas?

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From wikipedia's article on 2's complement (very worth a reading...):

"The two's-complement system has the advantage that the fundamental
arithmetic operations of addition, subtraction, and multiplication are
identical to those for unsigned binary numbers (as long as the inputs
are represented in the same number of bits and any overflow beyond those
bits is discarded from the result)"

That means that R = A (op) B

if (op) is + one possibility could be:

assign R = A + B;
assign Z = R == 32'h0;
assign N = R;
assign O = (A & B & (~R) | ((~A) & (~B) & R);

something like that

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Model a 32-bit ALU that can perform the following operations in
behavioral Verilog:

Control Lines           Operation
01                      Subtract
10                      Bitwise XOR
11                      Bitwise AND

This module has three inputs: two 32-bit signed numbers represented in
2'c complement format (A & B) and a 2-bit control (CTRL).  It produces
four outputs: a 32-bit result (R),  an overflow flag (O), a sign flag
(N), and a Zero flag (Z).  The result should be in 2's complement format
as well.  The overflow bit is set when the result of addition or
subtraction is out of range.  The sign flag is set when the result is
negative.  The zero flag is set when the result is zero.  Verify the
functionality of the model Using simulation. Use the following test
vectors for the simulation results that you submit:

A = FFFFFFF0   B = FFFFFFFF
A = FFFFFFFF   B = 000F00FF
A = 98998998   B = 12341234
A = AAAAAAAA   B = EFABCD12
A = FFFFFFFF   B = 00000001
A = FFFFFFFF   B = FFFFFFFF
A = FFFFFFFC   B = FFFFFFFC
A = FFFFFF00   B = 00000AB4
A = 00000025   B = 00080808

bitwise AND , bitwise XOR:

A = FFFFFFFF    B = 0A0AB0B0
A = ABCD4545    B = 12383588
A = F0F0F0F0    B = CFCFCFCF
A = 00000000    B = 11111111

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Actually, the inputs are given in 2's complement. How do I get the
output in 2's complement as well?

Should I do the regular conversion of the output to get 2's

And, how Do i get to know that the result is negative without
simulating?

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without simulating ? pencil+paper...

You didn't read my answer in post 2, or didn't understand it. There is

...
You say the numbers are 2's complement, it doesn't matter what they are
as long as you apply the right rules to operate and the interpret the
results.

Let's assume that you are using only 4 bits and that the MSB is the sign
bit:

If you say that your input is 2's complement, then the following table
applies:

binary | decimal representation (2's complement)
0000 | 0
...
0111 | 7
1000 | -8
...
1111 | -1

Now let's do add, ok ?

3 + 4 = 7
0011 + 0100 = 0111 ok ?
4 + (-1) = 3
0100 + 1111 = 0011 ok ?

Do you see what I meant in post 2 ?

Now, write some code and simulate it. (icarus verilog is very handy for
that)

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