Forum: FPGA, VHDL & Verilog Keeping Hierarchy in post-layout simulation using Microsemi designer

von Ioannis Sideris (Guest)

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   I am designing a system using Microsemi's tools. My design has a bug 
(as it seems) which only appears in post-layout simulation. The problem 
is that I have not found yet a way to keep the rtl hierarchy in 
post-layout simulation in order to detect the error. I have only managed 
to keep the hierarchy in structural simulation, but the error does not 
appear and the hierarchy is not preserved in post layout simulation. Do 
you know a way to keep the rtl hierarchy in post-layout simulation under 
Microsemi's design flow?

   Thank You
   Ioannis Sideris


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