EmbDev.net

Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
4 bit up down counter with a programmable modulo value Ahmed Alibrahim 8
Build an I2C protocol using systemverilog Fitrahhadi S. 3
Multi-core simulation in Modelsim Dima Ustinoff 2
Frequency Divider using VHDL _Jaiko 007 5
Verilog buffer implementation problem H Karim 1
Implement filter in verilog Qq Qq 1
CORDIC(Coordinate Rotation Digital Computer) CJU 3
troubles with VHDL testbench in Modelsim Dima Ustinoff 1
General variables Antonio Angelino 0
LUT in verilog Antonio Angelino 4
parallel data into serial rushin 1
Can't understand Verilog arithmetics Ubix2014 2
VHDL with ModelSim and Quartus II Rogério Clynton Ribeiro 0
VHDl for a custom CLB Johnny 0
Hello world on Atlys Spartan-6 xc6slx45 Slim Hmidi 3
Problems in constraining Negative setup slack Glen 3
Basic Question Elena Cososchi 2
control logic for memory selection felix89 2
OV7670 camera in VHDL jeorges FrenchRivera 6
Multiple posedges in sensitivity list Joe 6
VHDL calculator matrix input help. ed jones 1
Please help me in writing correct verilog test bench code for parallel crc32 with 32 bit data width Ajit Sinam 2
Arcade Centipede Game in Verilog Asiong Martinez 11
Bitwise OR of std_logic_vector Hamidreza Ahmadian 2
problem in 2d- dct computation Ajay Mittal 1
FATAL_ERROR: Iteration limit 10000 is reached Rohan Narkhede 7
DCT code. Don't know why it is not working. Ajay Mittal 2
recommend me an FPGA card for networking Nulik Nol 4
User Flash Memory, Machxo2 7000HE breakout ChrisChris 2
watermarking on FPGA Hamid Kavian 3
GPS to FPGA to PC Yuniarto Wimbo Nugroho 9
shift left or shift right deepak singh 9
Please Help! Not gate implementation nand Mihai Marius 2
Timing Requirements - Worst case Removal Slack Bryan 1
Interfacing FPGA with Global shutter camrea Mike 5
Blocking cammand Implementation Question guitardenver 9
RAM testing using VHDL Ritu Singh 0
help error 10822 vhdl daniel 1
Help with code for SPGA Vadhiraj 2
how to use clk in fsm daniel 2
8 bit serial to parallel Rushin thakkar 5
Parameterizing a data type in SystemVerilog/Verilog Joshua Vasquez 0
UART with Adder Maxim Moor 4
counting length of input signal in clock cycle units Counting length of input signal 1
VHDL synthesis result is not equal to behavioral Michal 4
Verilog VGA code HS VS timing Keny Joneyer 7
Can protocol to FPGA Ba Ehb 17
Connect 2 FIFOs and pass data [xillybus - VHDL] Junior Hpc 0
Does Verilog have generic map like VHDL? Sean Zheng 4
Voltage ThrEshold Adaptive Memristor in verilog Ronny Josef 0
Booting the PPC440 in virtex 5 processor from strata flash in ML507 development board Venkatesh 1