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Forum: FPGA, VHDL & Verilog troubles with VHDL testbench in Modelsim


troubles with VHDL testbench in Modelsim
von Dima U. (ustinoff)

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Hello everyone!

I have a problem: i've tried to simulate my project by the testbench, 
but Modelsim wrote next message:

Error: C:/.../testbench.vhd(62): (vcom-1136) Unknown identifier "arst".

And the same message for each other ports of testbench's component.

Also, next one type of messages, for internal signals of testbench:

Error: C:/.../testbench.vhd(63): (vcom-1484) Unknown formal identifier 
ARST_STIM

Top-entity "top_test" and each other entities in one common folder with 
testbench, so i do not understand what is a reason of the problem. I've 
posted the code of my testbench below:

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-- Created:

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--          by - Desmond.UNKNOWN (DESMOND-PC)

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--          at - 00:52:37 07.03.2016

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--

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LIBRARY ieee;

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USE ieee.std_logic_1164.all;

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ENTITY testbench IS

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END testbench;

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ARCHITECTURE rtl OF testbench IS

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   -- Architecture declarations

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   -- Internal signal declarations

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   -- Component declarations

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   COMPONENT top_test

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      PORT (

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         arst             : IN     std_logic;

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         bithigh          : IN     std_logic_vector(31 DOWNTO 0);

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         bitlow           : IN     std_logic_vector(31 DOWNTO 0);

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         ca_bh10          : OUT    std_logic;

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         ch_ca_data       : IN     std_logic_vector(31 DOWNTO 0);

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         ch_s             : IN     std_logic_vector(31 DOWNTO 0);

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         clk120MHz        : IN     std_logic;

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         clk240Mhz        : IN     std_logic;

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         clock_value_high : IN     std_logic_vector(31 DOWNTO 0);

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         clock_value_low  : IN     std_logic_vector(31 DOWNTO 0);

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         dac_1            : OUT    std_logic_vector(15 downto 0);

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         dac_2            : OUT    std_logic_vector(15 downto 0);

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         freq_setup       : IN     std_logic_vector(31 DOWNTO 0);

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         led              : OUT    std_logic;

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         level            : IN     std_logic_vector(31 DOWNTO 0);

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         out_symb         : OUT    std_logic;

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         pps              : IN     std_logic

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      );

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   END COMPONENT;

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--------------------------------------

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signal LED,CA_OUT,MOD_OUT : std_logic;

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signal ARST_STIM,CLK_120MHZ,CLK_240MHZ,PPS_STIM : std_logic := '0';

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signal BIT_HIGH_STIM,BIT_LOW_STIM,LEVEL_STIM,CA_DATA_STIM,FREQ_STIM,CLK_LOW_STIM,CLK_HIGH_STIM,CH_SELECT_STIM : std_logic_vector (31 downto 0);

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signal DAC_1, DAC_2 : std_logic_vector (15 downto 0);

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--------------------------------------

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constant CLK_120MHZ_PERIOD : TIME := 8.33 ns;

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constant CLK_240MHZ_PERIOD : TIME := 4.15 ns;

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-------------------------------------

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BEGIN

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 U_0 : top_test

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 PORT MAP (

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ARST_STIM => arst,

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CLK_120MHZ => clk120MHz ,

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CLK_240MHZ => clk240Mhz,

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PPS_STIM => pps,

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BIT_HIGH_STIM => bithigh ,

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BIT_LOW_STIM => bitlow,

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LEVEL_STIM => level, 

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CA_DATA_STIM => ch_ca_data,

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FREQ_STIM => freq_setup,

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CLK_LOW_STIM => clock_value_low,

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CLK_HIGH_STIM => clock_value_high,

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CH_SELECT_STIM => ch_s,

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DAC_1 => dac_1,

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DAC_2 => dac_2,

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CA_OUT =>  ca_bh10,

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LED => led,

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MOD_OUT => out_symb

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);

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--------------------------

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CLK_GENERATION : process

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begin

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CLK_120MHZ <= not CLK_120MHZ after (CLK_120MHZ_PERIOD/2);

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CLK_240MHZ <= not CLK_240MHZ after (CLK_240MHZ_PERIOD/2);

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end process CLK_GENERATION;

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----------------------------

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STIM_PROC : process

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begin

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ARST_STIM <= '1';

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PPS_STIM <= '0';

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wait for 100 ns;

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CH_SELECT_STIM <= (others=>'0');

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CLK_LOW_STIM <= "00010111010110001110001000011001";

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CLK_HIGH_STIM <= "00000000000000000000000000000001";

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FREQ_STIM <= "00000010001000100010001000100010";

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LEVEL_STIM <= "00000000000000000000000000110010";

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CA_DATA_STIM <= "00000000000000000000000000000110";

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BIT_LOW_STIM <= "00100110100101111011000000000000";

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BIT_HIGH_STIM <= "10101010010010111110100001010101";

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wait for 1800 ns;

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PPS_STIM <= '1';

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wait for 100 ns;

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PPS_STIM <= '0';

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wait for 1000 ns;

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CH_SELECT_STIM <= "00000000000000000000000000000001";

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wait for 999999000 ns;

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PPS_STIM <= '1';

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wait for 100 ns;

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PPS_STIM <= '0';

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wait for 10000000 ns;

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end process STIM_PROC;

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END rtl;


UPD: So, i understood: arts => ARST_STIM, and each other too.

  


  



  

  
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    Re: troubles with VHDL testbench in Modelsim
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Dima U. wrote:
> So, i understood: arts => ARST_STIM, and each other too.
Right. The assignment sequence inside the PORT MAP is
ComponentPort => ConnectingSignal

  


  




  

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