Forum: FPGA, VHDL & Verilog Bitwise OR of std_logic_vector

von Hamidreza A. (Company: Uni Siegen) (ahmadian)

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Suppose we have 4 buffer, each has a single bit which indicates if the 
buffer is empty and we connect this pin to the bellow signal.

signal buffer_empty       : std_logic_vector (3 downto 0);

Each bit of the above signal indicates whether the corresponding buffer 
is empty or not and the below signal indicates whether we have an empty 
buffer al all.

signal any_buffer_empty   : std_logic;

The second signal can be assigned as follows:

any_buffer_empty <= buffer_empty (0) and buffer_empty (1) and 
buffer_empty (2) and buffer_empty (3);

Now the problem gets difficult for me if the number of buffers is 
parameterized (by a generic or constant like NR_BUFF) and I cannot 
figure out how to calculate the second signal in this case.

Thanks in advance,

von Lothar M. (lkmiller) (Moderator)

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Hamidreza A. wrote:
> and I cannot figure out how to calculate the second signal in this case.
Check out the package reduce_pack and in there the functions or_reduce() 
as well as and_reduce().

See this also:

: Edited by Moderator
von Stefan Weide (Guest)

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You can also use the following
  -- bit-wise or
  any_buffer_empty <= '0' when buffer_empty=(buffer_empty'range=>'0') else
  --bit-wise and
  all_buffer_empty <= '1' when buffer_empty=(buffer_empty'range=>'1') else


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