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Verilog buffer implementation problem
von H Karim (Guest)

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Hey everyone,

I am writing a Verilog code to get 512 samples from an analog to digital 
converter IC (AD7266) and then stores them in a buffer. the ADC has got 
5 channels and the ADC_CH determines which channel should be sampled. 
when the buffer is filled this block of code asserts ADC_BUFFER_READY 
and waits for ADC_READ_ACK. If channel is changed then the buffer should 
be filled again.

The current issue is that when the channel is changed and filled again, 
some of the data in the buffer are still related to the old channel. I 
suspect there is something wrong with writing data to the buffer. i mean 
sometimes the new data is not written and the buffer keeps the old 
value.

for example:
1
ADC_memA[0] ch0

2
ADC_memA[1] ch0

3
ADC_memA[2] ch0

4
ADC_memA[3] ch0

5
.

6
.

7
ADC_memA[n]   ch1

8
ADC_memA[n+1] ch1

9
ADC_memA[n+2] ch1

10
.

11
ADC_memA[n+10] ch0

12
ADC_memA[n+11] ch0

13
ADC_memA[n+12] ch0

14
.

15
.

16
ADC_memA[511] ch0

17
18
19
Any Explanations? Why does this happen? 

20
21
// Shift register to capture the serial data from DIG_A port on positive edge 

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always@(negedge CLK) // changed from negedge CLK to posedge CLK 2/27/2015

23
begin

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        data_in_A[11]   <= data_in_A[10];

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        data_in_A[10]   <= data_in_A[9];

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        data_in_A[9]    <= data_in_A[8];

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        data_in_A[8]    <= data_in_A[7];

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        data_in_A[7]    <= data_in_A[6];

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        data_in_A[6]    <= data_in_A[5];

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        data_in_A[5]    <= data_in_A[4];

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        data_in_A[4]    <= data_in_A[3];

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        data_in_A[3]    <= data_in_A[2];

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        data_in_A[2]    <= data_in_A[1];

35
        data_in_A[1]    <= data_in_A[0];

36
        data_in_A[0]    <= DIG_A;

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        data_in_B[11]   <= data_in_B[10];

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        data_in_B[10]   <= data_in_B[9];

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        data_in_B[9]    <= data_in_B[8];

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        data_in_B[8]    <= data_in_B[7];

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        data_in_B[7]    <= data_in_B[6];

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        data_in_B[6]    <= data_in_B[5];

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        data_in_B[5]    <= data_in_B[4];

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        data_in_B[4]    <= data_in_B[3];

46
        data_in_B[3]    <= data_in_B[2];

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        data_in_B[2]    <= data_in_B[1];

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        data_in_B[1]    <= data_in_B[0];

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        data_in_B[0]    <= DIG_B;

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end

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always@(posedge CLK, negedge RESETn)

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begin

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  if ( RESETn == 1'b0) // GET RID OF XFER_RESET

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  begin

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    CSn               <= 1'b1; 

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        clk_cnt                 <= 4'b0;

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        FSM_read_state          <= ADC_Channel;

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        ADC_CH                  <= 3'b111; // invalid channel

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        channel_changed         <= 1'b0;

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        ch_cng_cnt              <= 0;

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  end

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    else

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    begin

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        case(FSM_read_state)

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        ADC_Channel: 

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        begin

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            sample_valid    <= 1'b0;

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            ADC_CH      <= DMA_ADC_CH;

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            if(ADC_CH == DMA_ADC_CH)

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                FSM_read_state  <= ADC_Select;

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            else

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            begin

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                channel_changed <= 1'b1;

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                ch_cng_cnt      <= 0;

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                FSM_read_state  <= ADC_Wait;

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            end

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        end

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        ADC_Wait: 

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        begin

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            FSM_read_state  <= ADC_Select;

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        end

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        ADC_Select: 

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        begin

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            CSn        <= 1'b0;

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            FSM_read_state  <= ADC_ReadBits;

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        end

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        ADC_ReadBits: 

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        begin

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            if(clk_cnt == 4'b1101)

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            begin

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                CSn      <= 1'b1;

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                clk_cnt     <= 4'b0;

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                // The AD7266 output coding is set to twos complement by selecting 2 × VREF range

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                sample              <= {~data_in_B[11], data_in_B[10:0], ~data_in_A[11], data_in_A[10:0]};

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                sample_ch           <= ADC_CH;

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                if(ch_cng_cnt == 32'd2000)

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                    channel_changed <= 1'b0;

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                else

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                    ch_cng_cnt      <= ch_cng_cnt + 1;

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                if(channel_changed == 1'b0)

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                    sample_valid        <= 1'b1;

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                FSM_read_state      <= ADC_Channel;

111
            end

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            else

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                clk_cnt     <= clk_cnt + 1;

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        end

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        endcase

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    end

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end

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reg last_sample;

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always@(posedge CLK160, negedge RESETn) 

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begin

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  if ( RESETn == 1'b0) 

125
  begin

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        FSM_buffer_state    <= BUFFER_Init;

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        cntr1               <= 4'b0;

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        first_ch            <= 3'b0;

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  end

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    else

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    begin

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        case (FSM_buffer_state)

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        BUFFER_Init:

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        begin

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            adc_buf_index       <= 0;

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            ADC_BUFFER_READY    <= 1'b0;

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            FSM_buffer_state    <= BUFFER_Record;

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        end    

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        BUFFER_Record:

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        begin

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            last_sample     <= sample_valid;

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            if(sample_valid == 1'b1 && last_sample == 1'b0)

146
            begin

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                ADC_memA[adc_buf_index]     <= {1'b0, ADC_CH, sample[23:12], cntr1[3:0], sample[11:0]};

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                FSM_buffer_state    <= BUFFER_Check;

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            end

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            else

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                FSM_buffer_state    <= BUFFER_Record;

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        end

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        BUFFER_Check:

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        begin

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            if(adc_buf_index == 9'b0)

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            begin

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                first_ch            <= sample_ch;

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                adc_buf_index       <= adc_buf_index + 1;

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                FSM_buffer_state    <= BUFFER_Record;

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            end

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            else if(adc_buf_index == 9'd511)

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            begin

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                cntr1   <= cntr1 + 1;

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                if(sample_ch == first_ch)

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                    FSM_buffer_state    <= BUFFER_Full;

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                else

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                    FSM_buffer_state    <= BUFFER_Init;    

169
            end

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            else

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            begin

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                adc_buf_index           <= adc_buf_index + 1;

173
                FSM_buffer_state        <= BUFFER_Record;

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            end    

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        end

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        BUFFER_Full:

178
        begin

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            ADC_BUFFER_READY    <= 1'b1;

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            if(ADC_READ_ACK == 1'b1 || channel_changed == 1'b1)

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                FSM_buffer_state    <= BUFFER_Init;

182
            else

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                FSM_buffer_state    <= BUFFER_Full;

184
            

185
        end

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        endcase

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    end

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end


  


  



  

  
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    Re: Verilog buffer implementation problem
  


  

    

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        Lothar M.
            (Company: Titel)
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H Karim wrote:
> for example:
Pls surround your Verilog code with the formatting tags (as described in 
the "manual" just above the edit-box). Or you attach simply a *.v 
Verilog file...
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