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Forum: FPGA, VHDL & Verilog Help with code for SPGA


von Vadhiraj (Guest)


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Hi,

I need a code to generate 4 different pulse signals, at same time. all 
are at frequency of 50Hz.
1st one starts after a delay of 0.01sec and ends at 0.011 sec.
2st one starts after a delay of 0.005sec and ends at 0.008 sec.
3st one starts after a delay of 0.01sec and ends at 0.015 sec.
4st one starts after a delay of 0.004sec and ends at 0.01 sec.

can any one help with the code.
all these signals are independent of each other. and have to be 
pulsating always.

von Vancouver (Guest)


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FPGA, I think?

Obviously you need a resolution of 1ms. Write a 5-bit counter that ist 
clocked at 1kHz. The first output is set to 1 between counter=10 and 
counter=11 and 0 else. The second output is set 1 between counter=5 and 
counter=8 and 0 else, etc. The counter is reset after counter=19, since 
your period is 20ms.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Vadhiraj wrote:
> can any one help with the code.
Which code?

> can any one help with the code.
First you must generate a "timertic" of 1ms.
Then you take a pattern of each timing:
signal_1 = "00000000001000000000"
signal_2 = "00000111000000000000"
signal_3 = "00000000001111100000"
signal_4 = "00001111110000000000"
With that you can simply run through those pattern with an index that is 
reset each 20ms.

> I need a code
No one here will do your homework. So you start with something and 
then we discuss the problems (if there are any).

> I need a code
Which language, what target and toolchain?
I could write that in C, Basic, VHDL and some more, but not in Verilog. 
So its essential neccessary to know your target.

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