shift left or shift right

Moderator (Company: Titel) #2664200
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deepak singh wrote:
> how can i use the command sla sra for this particular x...
You cannot use SLA and SRA for std_logic_vectors.
SLA and SRA are defined for bitvectors only.

> how can i shift left or shift right the data in vhdl.
> let i have x
>   constant x:std_logic_vector(7 downto 0):"01000101";
You cannot shift a constant.

So: what do you want to do?

This will work for a one bit shift:
1
  signal x:std_logic_vector(7 downto 0):"01000101";
2
  -- arithmetic right shift
3
  x <= x(7) & x(7 downto 1);
4
  -- arithmetic left shift
5
  x <= x(6 downto 0) & '0';
6
  -- logic right shift
7
  x <= '0' & x(7 downto 1);
8
  -- logic left shift
9
  x <= x(6 downto 0) & '0';
OP #2664259
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Dear Miller,
 what if i have a matrix
program as follows

library IEEE
...
...

Package matrix_types Is
Type matrix_4x1 Is Array (1 to 4) Of std_logic_vector (7 downto  0);
Type matrix_1x4 Is Array (1 to 4) Of std_logic_vector (7 downto  0);
Type matrix_4x4 Is Array (1 to 4, 1 to 4) Of std_logic_vector (7 downto 
0);
End Package matrix_types ;
...
...
architecture.......
begin
.....
process
.......

Variable x : matrix_4x1 :=
("000000100",
"0000000000",
"0011110000",
"0010110001");

begin

now i have to shift left or shift right EACH ROW of variable x TWICE or 
THRICE etc.

Please reply me dear miller...

Thanks and Best Regards,
Moderator (Company: Titel) #2666021
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> now i have to shift left or shift right EACH ROW of variable x TWICE or
> THRICE etc.
And from where comes the information about the shift count? Is that a 
constant? A "variable" shifter (lets say shift a byte by -7..+7) is not 
that simple! Because that results in a fairly BIG multiplexer...

> Please reply me dear miller...
Lets do it this way:
1. you show what you have,
2. you say what you want to achieve,
3. you report whats the problem with your description,
and then maybe
4. someone can help you...
Guest #4446745
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How do design a shift left circuit manually where the inputs a, which is 
an 8bit signal to be shifted, and ctrl which is a 3 bit signal 
specifying the amount to be shifted, Both are std_logic_vector type. 
using concurrent signal assignment, derive this circuit.


Hope you can help me. I really need help.
#4452457
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Sounds like a big multiplexer. As it is required to be done using 
concurrent signal assignment it looks like
1
result <= shift0 when sel = "000" else
2
          ...
3
          shift6 when sel = "110" else
4
          shift7;

By the way: Maybe it's not a good idea to resurrect 4 year old dead 
threads. Just do a new one.

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