Forum: FPGA, VHDL & Verilog counting length of input signal in clock cycle units

von Counting length of input signal (Guest)

Attached files:
  • spr.v (1.41 KB, 293 downloads)
  • spr_tb.v (1.03 KB, 313 downloads)

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Hello everyone!

My task is to write an up counter, that counts how long is the input 
signal (in) in clock (clk) cycle units from 1 to 1023 (precision 1 clock 
cycle). When input signal (in) ends, there has to be signal on wire 
ready, which means that data are ready to read and the value from the 
counter is now avaliable on data output. This value stays there until 
the end of the next input signal.

The whole project consists of 3 sequential processes: falling edge 
detector, counter and output register.

It has to be module with synchronous clock and asynchronous reset.

My problem here is that I don't reset the counter when input signal 

As an attachment I am posting my code for module and test bench.


von Andi (Guest)

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Your problem is that the counter is free running, and not only when the 
input pulse is high.
Eighter you make a pos-edge detector (in the same manner as the 
neg-edge) and reset the counter if the positive edge is detected.

Or you reset the counter while the ready signal is present and you 
enable the count up only if the pulse is high:

  if (ready) begin
    on_out <= count;
    counter <= 10'b0;

for that you need to have the counter code and the ready code in the 
same always() block, you can not write to counter in two different 

BTW: The following is useless, the counter anyway rolls over from 
1111111111 to 0000000000:

  if(count == 10'b1111111111)
    count <= 10'b0;

It would make more sense to stop the counter on all ones, so a too long 
pulse will always show the longest possible time.



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