FPGA, VHDL & Verilog

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Programmable logic

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FPGA development resources Pin Andreas S. 15
export port from altera qsys to verilog toplevel wrapper or fpga IO pins anonymous dude 1
Give a variable input to Spartan 3E Nirav Bhatt 1
The difference between test bench and test on DE1 board mrquan 1
bad synchronous description - ISE synthesis error Farzam 2
Max10 Application in CFM0 - Dualimage Eggi 1
why core current of Virtex or Spartan-II is so large? Ivan Abramovich 3
VHDL JK FlipFlop Error, Please help Locked D4N 005H 12
Speed up Modelsim Simulation Andy 7
ADC VHDL program pall 2
Alternatiive to reduce the number of logic elements in division Vik 2
quartus prime vs Xilinx ISE Payel Banerjee 1
Xilinx Virtex 5 FPGA evaluation board needed Nikolaos Athanasios Anagnostopoulos 6
Removing Latches Rob 5
uart fifo full Anan Hasasneh 3
Structural Model for 1-Bit ALU , VDHL code Anna Noukou 2
vhdl program of a digital clock & who have ideas to add button pls Saif Sabkhi 3
comparison of two unsigned std_logic_vectors Farzam 3
Programming a counter? Jessica Bobowski 12
Hardware-Software Partitioning on FPGA for communication receivers and network switches (webinar) Jegan 0
VHDL: Port map with std_logic_vector LiZhen Li 2
VHDL - 10% duty cycle Sen93 2
help in spi fpga Anan Hasasneh 9
3 bit output Ashuuu 3
query related to verilog code Thahseen 2
Spi Flash AT45DB321 Chris Customchris 11
Error in shift operator Hayder Al-Amily 0
8x1 Multiplexer Min_ah 7
Memory Interface with a Muxed Address/Data Bus Max 3
Altium NB3000 Moorthi 2
An overall PWM system by using FPGA _Jaiko007 5
Automated Verilog Module Instantiation Sauhaarda Chowdhuri 0
Machx02 User Flash Memory Chris Customchris 6
Blocking vs Non-blocking questions (verilog) Trevor Hill 1
8 bit DIVISION PROBLEM Marius Pop 1
VHDL parsing tool Bartlomiej T. 0
How to compare equivalent gate count, power consumption and possibly area and delay of circuits? Rohan Narkhede 0
BASYS 2 Implementation Nirav Bhatt 2
UART in FPGA for receiver rushin 27
Problem of Rom & sensitivity list Ed Hut 15
VHDL : signal goes to zero when looping on a state Ed Hut 11
Synchronizing reset signal used as a combinational logic Robert 3
16bit synchronous counter Ber 25 7
upcounter with enable signal for one clock cycle felix89 6
Clock port and any other port of a register should not be driven by the same signal source Robert 3
VHDL UART testbench that send/receive to/from a software on the Windows Mostafa Semofa 8
VHDL Button Debouncing Matt 18
Altera Quartus Design Assistant Critical Warnings Robert 1
modified booth encoder Pavithra Kodada 7
FPGA Frequency Divider _Jaiko 007 2
Dual processor Microblaze Ramzi Hmaidi 0
Incorrect reset in verilog Z. W. 3