help error 10822 vhdl

daniel Guest #4426225
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i will be thankful if somebody will can help me..
my aim is to make a block that get 3 inputs:
a clc that change every 0.1 sec
a input that get '1' every time i press key0
and reset button that reset my count

the aim is to count the number of time i press and when there is 3 secs 
that i dont press i get the count of the time i pressed
i tried to it with this code"
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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_unsigned.all;

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use ieee.std_logic_arith.all;

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entity CLAPNUM is 

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   port( 

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    resetN, clk : in std_logic;

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    key0         : in std_logic   ;

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    sinus      : out  std_logic_vector(4 downto 0));

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end CLAPNUM ; 

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architecture arc_CLAPNUM of CLAPNUM is 

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signal countera : std_logic_vector(4 downto 0) :="00000"  ;

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signal counterb : std_logic_vector(4 downto 0) :="00000" ;

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signal cinout   : std_logic := '0' ;

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signal moda   : std_logic := '0' ;

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begin 

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process ( resetN key0, clk)

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  begin

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    if resetN = '0' then

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    countera<="00000" ;

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    counterb<="11110";

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  elsif (key0 ='1') and moda='0' then

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    countera<= countera+"00001" ;

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    counterb<="11110";

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  elsif (rising_edge(clk))  then

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    if counterb/="00000" and (key0 ='0') then

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      counterb <= counterb-"00001";

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    else      

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      moda <= '1';

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    end if;

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  elsif moda='1' then

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  sinus<= countera;

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  end if;

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   end process;

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end arc_CLAPNUM;


but clearly it dosent work...
can someone help me plz?
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Lothar M. Moderator (Company: Titel) #4426340
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First have a look at the attached sreenshot...

> but clearly it dosent work...
And HOW did you see that?
Did you do a SIMULATION?
What ERROR messages or WARNINGS did you get?
And why do you ignore them all?

In fact the problem here is the well known and famous "combinatorial 
loop":
as long as key0 is 1 and moda is 0 the countera is counting upwards 
without any clock at maximum and random speed:
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  elsif (key0 ='1') and moda='0' then

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    countera<= countera+"00001" ;

Try Google translator on that:
http://www.lothar-miller.de/s9y/archives/42-Kombinatorische-Schleifen.html

Let me ask you: where did you see this structure in literature?
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begin process ( resetN key0, clk)

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begin

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if resetN = '0' then

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  ...

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elsif (key0 ='1') and moda='0' then

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  ...

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elsif (rising_edge(clk)) then

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  ...

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end if;

There's only one way to desrcibe a synchronous process:
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begin process ( resetN, clk)

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begin

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if resetN = '0' then

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  ...

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elsif (rising_edge(clk)) then

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  ...

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end if;


Beside the whole things above: the sensitivity list is incomplete, moda 
ist missing. Therefore a simulation will show wrong results...

BTW: congratulations to use the 1-process-FSM. You are a big step 
further than in the thread https://embdev.net/topic/386779
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