Hi.. Im newbie in FPGA(2 weeks). i've tried to build an I2C protocol 
using Sytemverilog. Well my design is based on i2c timing diagram but 
i'm not sure whether it is correct or not. However, i've already 
simulated using Modelsim and im quite happy with the result. Well the 
problem is why the result is different to simulation? FYI: Im using 
Quartus software (Altera based) and the FPGA board is De0-nano from 
Terasic. I'm glad if anyone give me a respond to my problem. Thankyou.

This is my coding.


//i2c as Master
module i2cprotocol (inout SDA, output logic SCL, output logic [7:0]DATA, 
input clk);

logic SDA_Utopia ;
logic [4:0] num;
assign SDA = SDA_Utopia;

always
begin
 i2c_start();
 i2c_write(8'hA0);
 i2c_write(8'h00);
 i2c_write(8'hA1);
 i2c_stop();
end

task i2c_start();
@(posedge clk);
SDA_Utopia <= 1'b1;
SCL<= 1'b1;
@(posedge clk);
SDA_Utopia <= 1'b0;
SCL <= 1'b1;
@(posedge clk);
SDA_Utopia <= 1'b0;
SCL <= 1'b0;
endtask


task i2c_stop();
@(posedge clk);
SDA_Utopia <= 1'b0;
SCL <= 1'b1;
@(posedge clk);
SDA_Utopia <= 1'b1;
SCL <= 1'b1;
endtask

task i2c_write(input logic [7:0] data); //data 8-bit
for(num=0;num<=8;num++)       //7 bit-Address
begin
@(posedge clk or negedge clk);
  if (num == 8)
    begin
    SDA_Utopia <= 1'b0; //1-bit ACK
   SCL <= 1'b0;
    end
    else
    begin
    SDA_Utopia <= data[7-num];
    SCL <= 1'b0;
    end

    @(posedge clk or negedge clk);
    SCL <= 1'b1;
    @(posedge clk or negedge clk);
    SCL <= 1'b0;

  end
  num = 0;
endtask

task i2c_read(output logic [7:0] data_out, input logic ACKNACK);
  for(num=0;num<=8;num++)       //7 bit-Address
  begin
  @(posedge clk or negedge clk);
     if (num == 8)
        begin
        SDA_Utopia <= ACKNACK; //1-bit ACK
        SCL <= 1'b0;
        end
        else
        begin
        data_out[7-num ]<=SDA;
        SCL <= 1'b0;
        end

    @(posedge clk or negedge clk);
    SCL <= 1'b1;
    @(posedge clk or negedge clk);
    SCL <= 1'b0;
  end
   num = 0;
endtask



endmodule




Subchan