GPS to FPGA to PC

Yuniarto Wimbo N. wrote:
> Hello i want send data NMEA from GPS to FPGA and from FPGA to PC, i'm
> using UART vhdl with 38400 baudrate.
Why the FPGA? I would connect the GPS directly to the PC...

> i test uart
Which one?

> i test uart with send n receive data, if i send data one alphabet
> example "a" or one number example "8" uart is work
How did you find that out?
And how did you test it?
Did you test this uart an a testbench in a simulator?

> but if i send data nmea from GPS like
> "$GPVTG,054.7,T,034.4,M,005.5,N,010.2,K*48" i cant receive it in my PC.
This somehow curios design seems to be extremely simple to me. In VHDL 
it will be somewhat like that:

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  PCout  <= GPSin;

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  GPSout <= PCin;

> any help me please.
Without knowing anything about your desgin, even not seeing one line of 
HDL, how should anyone be able to help?

>Why the FPGA? I would connect the GPS directly to the PC...
-because i want made autopilot system using FPGA

>How did you find that out?
>And how did you test it?
>Did you test this uart an a testbench in a simulator?
- i find result di my pc
- i test fpga to pc using

this is my uart

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 TX Modul:

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_arith.all;

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use ieee.std_logic_unsigned.all;

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entity TX is

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port(s_out:out std_logic;

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    p_in:in std_logic_vector(7 downto 0);

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    go:in std_logic;

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    clk:in std_logic);

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end TX;

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architecture UARTtx of TX is

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signal clk9600:std_logic:='0';

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begin

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  process(clk)

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  variable count:integer range 0 to 1300:=0;

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  begin

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    if clk='1' and clk'event then 

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      if count>=650 then count:=0;clk9600<=not clk9600;

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      else count:=count+1;

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      end if;

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    end if;

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  end process;

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  process(clk9600,go,p_in)

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  variable cnt:integer range -2 to 90:=0;

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  variable buf:std_logic_vector(9 downto 0):="1010000010";

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  variable stop:std_logic;

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  begin

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    if clk9600='1' and clk9600'event then 

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      if go='1' then

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        buf(8 downto 1):=p_in;

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        if cnt=0 then s_out<='0';cnt:=1;

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        elsif cnt=1 then s_out<=p_in(0);cnt:=2;

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        elsif cnt=2 then s_out<=p_in(1);cnt:=3;

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        elsif cnt=3 then s_out<=p_in(2);cnt:=4;

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        elsif cnt=4 then s_out<=p_in(3);cnt:=5;

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        elsif cnt=5 then s_out<=p_in(4);cnt:=6;

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        elsif cnt=6 then s_out<=p_in(5);cnt:=7;

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        elsif cnt=7 then s_out<=p_in(6);cnt:=8;

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        elsif cnt=8 then s_out<=p_in(7);cnt:=9;

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        elsif cnt=9 then s_out<='1';

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        end if;

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      else cnt:=0;

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      end if;

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    end if;

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  end process;

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end UARTtx;

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RX Modul:

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_arith.all;

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use ieee.std_logic_unsigned.all;

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entity RX is

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port(s_in:in std_logic;

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    p_out:out std_logic_vector(7 downto 0):=X"00";

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    clk:in std_logic);

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end RX;

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architecture UARTs of RX is

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signal cnt:integer range 0 to 25:=0;

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signal buff:std_logic_vector(7 downto 0):=X"00";

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signal start:std_logic:='0';

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signal clk9600:std_logic:='0';

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begin

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  process(clk)

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  variable count:integer range 0 to 1300:=0;

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  begin

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    if clk='1' and clk'event then 

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      if count>=650 then count:=0;clk9600<=not clk9600;

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      else count:=count+1;

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      end if;

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    end if;

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  end process;

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  process(s_in,clk9600,cnt)  

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  begin

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    if clk9600='0' and clk9600'event then 

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      if cnt>=9 and s_in='1' then cnt<=0;

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      --if cnt>=9 and s_in='0' then cnt<=0;

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      elsif start='1' and cnt<=20 then cnt<=cnt+1;

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      end if;

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    end if;

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    if s_in='0' and cnt=0 then start<='1';

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    elsif cnt>=9 and s_in='1' then start<='0';

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    --elsif cnt>=9 and s_in='0' then start<='0';

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    end if;  

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  end process;

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  process(s_in,cnt,clk9600)  

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  begin

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    if cnt>=1 and cnt<=8 and clk9600='1' then

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      buff(cnt-1)<=s_in;

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    end if;    

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  end process;

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  p_out<=buff when start='0';  

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  --p_out<=X"F0";

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end UARTs;

>so a single character works, but a sequence of characters is not
>received? Does "not received" mean, that you get no data at all or do
>you receive scrambled data?

>Maybe you send the individual characters of your NMEA-string too close
>to each other, so that there's not enough time for a stop-bit inbetween.
>Take a look to the bit-sequence with an oscilloscope and decode the
>first 2-3 characters manually, that may tell you what you have to fix.

yes you true, i have receive scramble data, and data not constants per 
second

Yuniarto Wimbo N. wrote:
> this is my uart
1. See the screenshot.
2. Read it and understand it.
2. Do it.


There are too much signals in the sensitivity list:
>   process(clk9600,go,p_in)
clk9600 would be enough.
But: clk9600 ist NOT a clock, is is just a simple clock enable...

> i have receive scramble data, and data not constants per second
As I saw that code my first thought was: Ouch!

You MUST implement a test bench an check your design on that test bench. 
Then you can see that whole bunch of tricky race conditions in your 
code. One is e.g. the sampling point of the incoming RS232 signal.

At the last link there you can find a test bench:
http://www.lothar-miller.de/s9y/archives/60-RS232-IO.html#extended
And also look there:
http://www.lothar-miller.de/s9y/categories/42-RS232
(Try Google translator, its German...)

>Achim S. (Guest)
(clk9600) is just name only not value baudrate. :D
thanks a lot for your guide, ok i want correct my programming again.
:D

> Lothar Miller
i'm sorry about my post :) please forgive me about it.

ok i'll implement uart vhdl programming in testbench.

Yuniarto Wimbo N. wrote:
> (clk9600) is just name only
But you use it as a clock, because everything using a 'event or a 
rising_edge() or a falling_edge() is a clock...  :-o

Some simple rules for beginners:
- only 1 clock in the whole design (thats usually around 10..100MHz)
- external signals must be synced to that clock before using them
- no variables, or at the very least no memorizing variables
- no latches (read the synthesizers warnings!)