library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

        entity moore_sqrt is
port (clk : in std_logic;
      enable : in std_logic;
      input : in std_logic_vector (15 downto 0);
      data_ready : out std_logic;
      output : out std_logic_vector (31 downto 0)
  );
end moore_sqrt;

architecture behavioral of moore_sqrt is
------------------------------------------------------------
function  division  (x : std_logic_vector; y : std_logic_vector) return std_logic_vector is
variable a1 : std_logic_vector(x'length-1 downto 0):=x;
variable b1 : std_logic_vector(y'length-1 downto 0):=y;
variable p1 : std_logic_vector(y'length downto 0):= (others => '0');
variable i : integer:=0;
    begin
        for i in 0 to y'length-1 loop
            p1(y'length-1 downto 1) := p1(y'length-2 downto 0);
            p1(0) := a1(x'length-1);
            a1(x'length-1 downto 1) := a1(x'length-2 downto 0);
            p1 := p1-b1;
            if(p1(y'length-1) ='1') then
                a1(0) :='0';
                p1 := p1+b1;
            else
                a1(0) :='1';
            end if;
        end loop;
return a1;
end division;
-------------------------------------------------------------- 
type state_type is (s0, s1, s2, s3, s4, s5, s6);  --type of state machine
signal current_state,next_state: state_type;  --current and next state declaration

signal xk : std_logic_vector (31 downto 0);
signal temp : std_logic_vector (31 downto 0);
signal latched_input : std_logic_vector (15 downto 0);
signal iterations : integer := 0;
signal max_iterations : integer := 10;  --corresponds with accuracy

begin

process (clk,enable)
begin
if enable = '0' then
    current_state <= s0; 
elsif clk'event and clk = '1' then
    current_state <= next_state;   --state change
end if;
end process;

--state machine
process (current_state)
begin
  case current_state is
    when s0 =>          -- reset       
        output <= "00000000000000000000000000000000";
        data_ready <= '0';
        next_state <= s1;
    when s1 =>          -- latching input data
        latched_input <= input;
        next_state <= s2;        
     when s2 =>         -- start calculating
        -- initial value is set as a half of input data
        output <= "00000000000000000000000000000000";
        data_ready <= '0';
        xk <= "0000000000000000" & division(latched_input, "0000000000000010");
        next_state <= s3;
        iterations <= 0;
    when s3 =>         -- division
        temp <= division ("0000" & latched_input & "000000000000", xk);
        next_state <= s4;
    when s4 =>          -- calculating 
        if(iterations < max_iterations) then
            xk <= xk + temp;
            next_state <= s5;
            iterations <= iterations + 1;
        else
            next_state <= s6;
        end if;
    when s5 =>          -- shift logic right by 1
            xk <= division(xk, "00000000000000000000000000000010");
            next_state <= s3;       
    when s6 =>             -- stop - proper data
--          output <= division(xk, "00000000000000000000000001000000");  --the nearest integer value
            output <= xk;    -- fixed point 24.6, sqrt = output/64;
            data_ready <= '1';
    end case;
end process;
end behavioral;