Parameterizing a data type in SystemVerilog/Verilog

Hi all,

I have a data structure that I'm building, and I'm wondering if it's 
possible to parameterize the datatype to be unsigned or signed.


Here's an example of what I'd imagine (although it's not valid syntax)

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module myModule

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# (parameter UNSIGNED = 1)

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    generate

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        if (UNSIGNED == 1)

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            input logic [7:0] my_bus;

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        else

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            input logic signed [7:0] my_bus;

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    endgenerate)

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// data structure guts here

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endmodule

Is something like this possible?

Thanks for taking a look!