Hi guys,
I have another question about verilog use, and I don't have someone to 
ask to.
The question is about variables used by different modules in the same 
project, but not always modules modify them. How can I define those 
variables? Maybe in the complete project I should define it and simply 
put those as input to modules. And, if modules sometimes don't modify 
these variables, it's enough to declare them as "reg"  in the modules?

I know it is a simple question, I hope nobody will get angry.

thanks.