Can protocol to FPGA

Thank you for the response.
If i use an Ip core ( i found one in opencores) can I use directly the 
gpio's of the fpga or i have to add an external composant to communicate 
with the protocol can ?

Ba E. wrote:
> can I use directly the gpio's of the fpga
No, because the CAN interface is much more "analog" than the FPGA IO 
drivers. As already said: you must adapt the different physics by using 
a CAN transceiver. Additionally with a transceiver you get an EMV and 
ESD robust interface too.

I found an FPGA including two CAN's here :
http://www.devboards.de/en/home/boards/product-details/article/dbc5cefa7/

Now, with the transeiver that Frank gave, I Have to link a transeiver to 
the FPGA as a CAN bus ? ( for 4 CAN bus , 4 transeivers ? )

Ba E. wrote:
> I found an FPGA including two CAN's here
Indeed you did find a BOARD with a FPGA and "2 CAN Transceiver" on it. 
There's is NO (in numbers 0) CAN controller inside the FPGA. You 
must implement 2 CAN controllers and connect them to the transceivers.

And when that is done you simply wire two additional transceivers to the 
FPGA (in the same manner as the two on the board). Finally you implement 
two additional CAN cores in the FPGA. Then you're done...

So the very first step is to implement 1 core in the FPGA and connect it 
to 1 of those transceivers.

Ah okey , I start to understand a little bit what you sayin guys. Really 
thank you.

So I restate my probleme ( I attached a diagram to be clearer ): i want 
my FPGA have 2 inputs of data ( that transmitted in protocole CAN) and 2 
outputs of data ( that will be transmitted ine protocole CAN ) I thought 
that it possible to emulate a bus CAN without adding anything to the 
FPGA only using GPIO's and you said it's not possible. What about the RX 
TX of fpga solution to emulate a CAN Bus ( without adding external 
coposants) ?

Also ,  I don't know if it's possible to use only internal ressources of 
the fpga to emulate can bus ?

Ba E. wrote:
> i want my FPGA have 2 inputs of data ( that transmitted in protocole
> CAN) and 2 outputs of data ( that will be transmitted ine protocole CAN )
Why do you split that up? CAN is a Bidirectional-Multi-Master-Bus.

> What about the RX  TX of fpga solution to emulate a CAN Bus
Each of the FPGA cores will have a TX output and a RX input. The CAN 
transceiver will make CANH and CANL out of those signals. The CAN bus 
itself is based on CANH and CANL as the physical layer. The IO ports of 
an FPGA is not able to generate those CAN bus signals without additional 
hardware reliably. That starts with the IDLE level which is differential 
0V. Simply startt reading about signal levels on a CAN bus and compare 
them with the capabilities of the IO pin drivers.

> Also , I don't know if it's possible to use only internal ressources of
> the fpga to emulate can bus ?
Do you want to have 4 real physical CAN busses to connect real physical 
devices or do you only want to "emulate" or "simulate" something?

> if it's possible to use only internal ressources of the fpga
No. To get a real CAN Bus with CANH and CANL you MUST use a transceiver. 
Why the heck don'T you simply connect such two transceivers for small 
money to the FPGA. Thats only 4 wires plus supply in total...

-gb- wrote:
> got an Spartan3 FPGA Baord with CAN transciever. It is a Celoxica RC10.
That borad only has 1 CAN transceiver. The DBC5CEFA7 usesd by Ba Ehb has 
2 transceivers. But he wants 4. So what to do?

Frank wrote:
> if you need 4 independent CAN-Bus lines, then the schematic should look
> like in the attached picture
I added to the schematic some signal names for clarity.

Thank you all for your responses. It's very helpful and it clarified 
things to me.

So , I understand that i have to use transceivers like Lothar Miller & 
Frank said. in the diagram the transceiver is connected to the fpga 
using RX/Tx ports of the Fpga. Now my question is : Is an FPGA have a 
limited numer of RX/TX ports ? ( because if I need 4 Can busses then i 
will use 4 transcievers that will have to be connected to 4 Rx/tx ports 
)

There is an FPGA with like 10 Rx/Tx ports to connect 10 transceivers ? ( 
in reality i need 10 Can busses , i just said 4 to understand )

The Rx/Tx ports of the Fpga are the RS232 port ?

Can the transcievers just be connected to the fpga using GPIO's ?


>Why do you split that up? CAN is a Bidirectional-Multi-Master-Bus.
I don't want t split I just wasn't clear.

Ba E. wrote:
> The Rx/Tx ports of the Fpga are the RS232 port ?
No. As already stated the RX and TX are signals on simple IO pins of the 
FPGA. And there is no kind of RS232 port involved in the whole system at 
all. That mentioned RX and TX signals are the receive input and the 
transmit output of the CAN IP core inside the FPGA. Every (or at least 
nearly every) IO pin of the FPGA could be RX or TX...

> There is an FPGA with like 10 Rx/Tx ports to connect 10 transceivers ? (
> in reality i need 10 Can busses , i just said 4 to understand )
As I already said: implement ONE (in numbers 1) CAN interface. Then have 
a look how much resources it needs in the FPGA. Then have a look for a 
FPGA that provides at least 10 times that resources (plus some more or 
less demanding logic you will need additionally to serve those 10 CAN IP 
cores).

But first start with 1 CAN interface. Thats the very first step.


BTW: why in all the world do you need a node with 10 CAN interfaces in 1 
design?