Forum: FPGA, VHDL & Verilog parallel data into serial

von rushin (Guest)

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hello there i have made code for converting parallel data into serial 
data. i have attached my main file and test bench file. can you help 
me??. but it is not giving me correct data . can you help me??

von Lothar M. (lkmiller) (Moderator)

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rushin wrote:
> but it is not giving me correct data
What do you expect? And what do you get instead?

> i have attached my main file and test bench file
The attached code is almost unreadable! You MUST use identation to get 
readable code. No one wants to dig through a wild heap of ASCII 

All in all that code looks like an software programmer trying to 
program an FPGA. But you must get the point: VH-D-L ist not VH-P-L. It 
is a description language, noct a programming language. And to 
describe something you must have a picture or a kind of sketch to look 
at. Or at least you must have some kind of picture in your mind. Then 
you can describe what you see.

Or the other way: when I hear "PISO" then I see a multiplexer or a shift 
register in mind. And now I can start to describe that thing...

A hint: think about the names of your signals and ports. Its disturbing 
to see somewhat like that:
serial_din1:OUT STD_LOGIC;
A input which is an OUT? Kind of strange...

Look there: http://www.lothar-miller.de/s9y/categories/26-SPI-Slave
Its SPI and in SPI the MISO is a Parallel In Serial Out...


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