Does Verilog have generic map like VHDL?
Guest
#4409078
I am a beginner of Verilog. I am trying to build an N-bit-comparator. But I found no information for any generic map. I know in VHDL I can do generic (N: integer:=4); so that I can modify bits when I want to use this block. If there is anything in Verilog that is similar to generic map in VHDL, it will help save me lots of work.
Guest
#4409086
googled: verilog generic http://www.asic-world.com/verilog/para_modules1.html sufficient explaination for you?
Guest
#4409088
It is called parameter
Instanziated it is like this:
Guest
#4409126
Thank you! My problem's solved now!
Guest
#4409128
@Lattice, Thank you! Now I understand very clear! Reply |