Hi everyone,
I have a basys2 digilent fpga card. I just want to draw a picture on the
screen with VGA cable. The following is the code that I wrote. However,
it is not working that I expect. Could you please help me about where
the problem is? Thanks ..
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//////////
// Company:
// Engineer:
//
// Create Date: 15:41:47 05/18/2013
// Design Name:
// Module Name: kodilk
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
//////////
module basla(clr,clk,hsync,vsync,red,green,blue);
input wire clr;
input wire clk; // This is for 50Mhz clock signal . Connect B8 pin
output wire hsync; //horizontal sync out
output wire vsync; //vertical sync out
output reg [2:0] red; //red vga output
output reg [2:0] green; //green vga output
output reg [1:0] blue; //blue vga output
// This block is reponsible of 25 Mhz clock generation.
reg clk_pixel=0;
always @ (posedge clk)
begin
clk_pixel <= ~clk_pixel ; // clk_pixel is equal to 50/2=25 Mhz.
end
// Counting mechanism
reg [9:0] hc;
reg [9:0] vc;
always @(posedge clk_pixel or posedge clr)
begin
if (clr == 1)
begin
hc <= 0;
vc <= 0;
end
else
begin
if (hc < 799)
hc <= hc + 1;
else
begin
hc <= 0;
if (vc < 524)
vc <= vc + 1;
else
vc <= 0;
end
end
end
// end of counting mechanism
//sync pulses - active low-
assign hsync = (hc < 96) ? 0:1;
assign vsync = (vc < 2) ? 0:1;
// lets draw some picture
always @ (hc or vc)
begin
if (vc >34 && vc < 515)
begin
if (hc > 143 && hc < 700)
begin
red = 3'b111;
green = 3'b000;
blue= 2'b00;
end
end
end
endmodule
Plus , ucf file:
CE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "blue[0]" LOC = "H13" ;
NET "blue[1]" LOC = "J13" ;
NET "clk" LOC = "B8" ;
NET "clr" LOC = "N3" ;
NET "green[0]" LOC = "F14" ;
NET "green[1]" LOC = "G13" ;
NET "green[2]" LOC = "G14" ;
NET "hsync" LOC = "J14" ;
NET "red[0]" LOC = "C14" ;
NET "red[1]" LOC = "D13" ;
NET "red[2]" LOC = "F13" ;
NET "vsync" LOC = "K13" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE