# EmbDev.net

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Hello everybody! I need some help. I use VHDL language and ModelSim PE
Student Edition. I nade to build some elementary gates: not, or, xor,
and, mux mux, dmux, 16 bit variants not16 and16 and multiway variants
mux8way16 etc from nand gates. I made some schematics on paper and
logic. Ex. Not imp. Nand : (a Nand b) Nand (a Nand b).
My first gate i want to buils is Not gate. (a nand a), for this i make
this code:
 1 library IEEE;  2 use ieee.std_logic_1164.all;  3 4 entity noot is  5  port (a : in std_logic;  6  cout : out std_logic  7  );  8 end noot;  9 10 architecture behavior of noot is  11  component naand  12  port(  13  a1 : in std_logic;  14  b1 : in std_logic;  15  );  16  end component;  17 18  NA1 : naand port map (  19  a1 =>a,  20  b1 =>a,  21  out1 => cout  22  ); 
so here is my problem, how i can do the function of nand?
it was simple to write:
 1   2  cout<= a nand a; 
but i want later to add more nand gates in separate bloks
i try with signal
 1 signal s1, s2 : std_logic := '0'; or without ":= '0'"  2  NA1 : naand port map (  3  a1 =>s1,  4  b1 =>s2,  5  out1 => cout => s1 nand s2  6  ); 
How i can make this to work?

This is schematic of wat i want:
 1   2  NOT GATE  3  ____________________________  4  | ________ |  5  | _____| \ |  6  a | / | \ | cout  7 -----------|----= | NAND |-----|-------  8  | \_____| / |  9  | |________/ |  10  |____________________________| 

: Edited by Moderator

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Mihai M. wrote:
> I use VHDL language
Pls have a look at the screenshot...

> component naand
That component has no output. Its useless and will be optimized away.

> out1 => cout => s1 nand s2
What should this do?
In a port map you ca assign 1 port to 1 signal.
> How i can make this to work?

> This is schematic of wat i want
I'm not able to figure out your problem... :-/

> so here is my problem, how i can do the function of nand?
Try it this way and think about it...
 1 library IEEE;  2 use ieee.std_logic_1164.all;  3 4 entity naand is  5  port (a1,b1 : in std_logic;  6  out1 : out std_logic);  7 end noot;  8 9 architecture behavior of naand is  10 begin  11  out1 <= a1 nand b1;  12 end behavior;  13 14 15 16 library IEEE;  17 use ieee.std_logic_1164.all;  18 19 entity noot is  20  port (a : in std_logic;  21  cout : out std_logic  22  );  23 end noot;  24 25 architecture behavior of noot is  26  component naand  27  port (a1,b1 : in std_logic;  28  out1 : out std_logic);  29  end component;  30 31  NA1 : naand port map (  32  a1 => a,  33  b1 => a,  34  out1 => cout  35  );  36 end behavior; 

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Well,  i want to make that component naand to function like a nand gate,
thx for the information.

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