Hi all,

I am newly working with Cosmos OpenSSD, a real SSD Board that deploys 
the flash Storage Controller and the Error Correction Code on FPGA. The 
Software is C++, yet the firmware is VERILOG. It is my first time 
working with Verilog and for now I only want a small trick in order to 
test a hypothesis.

My question is:

Let's say I have

1

assign nxt_parity[i] = cur_parity[i-1];

I want nxt_parity vector to have only 1s, independent of cur_parity. Can 
I do this trick in the assign?

1

parameter PARITY_ONE = 1;

2

assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE));

Thank you very much for any hint you may provide!

best,
Elena