I want to build a final state machine embodies eight numbers and then she proceeded to tell the eighth. For example if the eight number is four I want the machine extract four pulses of 1 clock cycle difference between between pulses and then wait another 10 clock cycles and then switches to the next state( and in the next do the same thing). The problem that he dosent let me use the clock in the states .. Does anyone have an idea what to do? The code

1 | library ieee; |

2 | use ieee.std_logic_1164.all; |

3 | use ieee.std_logic_unsigned.all; |

4 | use ieee.std_logic_arith.all; |

5 | |

6 | entity pulsim is |

7 | port( |

8 | resetN, clk : in std_logic; |

9 | da : in std_logic_vector(3 downto 0) ; |

10 | db : in std_logic_vector(3 downto 0) ; |

11 | dc : in std_logic_vector(3 downto 0) ; |

12 | dd : in std_logic_vector(3 downto 0) ; |

13 | de : in std_logic_vector(3 downto 0) ; |

14 | df : in std_logic_vector(3 downto 0) ; |

15 | dg : in std_logic_vector(3 downto 0) ; |

16 | dh : in std_logic_vector(3 downto 0) ; |

17 | sinus : out std_logic); |

18 | end pulsim ; |

19 | architecture behavioral of pulsim is |

20 | |

21 | |

22 | type state_type is (s0,s1,s2,s3,s4,s5,s6,s7); |

23 | signal current_s,next_s: state_type; |

24 | signal countera : std_logic_vector(4 downto 0) :=dh &'0' ; |

25 | signal counterb : std_logic_vector(4 downto 0) :="01010" ; |

26 | signal cinout : std_logic ; |

27 | |

28 | ```
begin
``` |

29 | |

30 | process ( resetN , clk) |

31 | ```
begin
``` |

32 | if resetN = '0' then |

33 | current_s <= s0; |

34 | elsif (rising_edge(clk)) then |

35 | current_s <= next_s; |

36 | end if; |

37 | end process; |

38 | |

39 | |

40 | process (current_s,dh,clk) |

41 | ```
begin
``` |

42 | sinus <= cinout ; |

43 | case current_s is |

44 | when s0 => --when current state is "s0" |

45 | if(dh ="1111") then |

46 | cinout <= '0'; |

47 | next_s <= s0; |

48 | ```
else
``` |

49 | if clk='1' then |

50 | if countera /= "00000" then |

51 | countera <= countera-"00001"; |

52 | cinout<= not(cinout); |

53 | counterb<="01010"; |

54 | |

55 | elsif (countera = "00000") and (counterb/="00000") then |

56 | counterb <= counterb-"00001"; |

57 | cinout <= '0' ; |

58 | ```
else
``` |

59 | counterb<="01010"; |

60 | countera<=dg &'0'; |

61 | next_s <= s1; |

62 | end if; |

63 | end if; |

64 | end if; |

65 | when s1 => |

66 | |

67 | if rising_edge(clk) then |

68 | if countera /= "00000" then |

69 | countera <= countera-"00001"; |

70 | cinout <= not (cinout) ; |

71 | counterb<="01010"; |

72 | |

73 | elsif (countera = "00000") and (counterb/="00000") then |

74 | counterb <= counterb-"00001"; |

75 | cinout <= '0' ; |

76 | ```
else
``` |

77 | counterb<="01010"; |

78 | countera<=df &'0'; |

79 | next_s <= s2; |

80 | end if; |

81 | end if; |

82 | |

83 | |

84 | when s2 => |

85 | |

86 | if rising_edge(clk) then |

87 | if countera /= "00000" then |

88 | countera <= countera-"00001"; |

89 | cinout <= not (cinout) ; |

90 | counterb<="01010"; |

91 | |

92 | elsif (countera = "00000") and (counterb/="00000") then |

93 | counterb <= counterb-"00001"; |

94 | cinout <= '0' ; |

95 | ```
else
``` |

96 | counterb<="01010"; |

97 | countera<=de &'0'; |

98 | next_s <= s3; |

99 | end if; |

100 | end if; |

101 | |

102 | when s3 => |

103 | |

104 | if rising_edge(clk) then |

105 | if countera /= "00000" then |

106 | countera <= countera-"00001"; |

107 | cinout <= not (cinout) ; |

108 | counterb<="01010"; |

109 | |

110 | elsif (countera = "00000") and (counterb/="00000") then |

111 | counterb <= counterb-"00001"; |

112 | cinout <= '0' ; |

113 | ```
else
``` |

114 | counterb<="01010"; |

115 | countera<=dd &'0'; |

116 | next_s <= s4; |

117 | end if; |

118 | end if; |

119 | |

120 | when s4 => |

121 | |

122 | if rising_edge(clk) then |

123 | if countera /= "00000" then |

124 | countera <= countera-"00001"; |

125 | cinout <= not (cinout) ; |

126 | counterb<="01010"; |

127 | |

128 | elsif (countera = "00000") and (counterb/="00000") then |

129 | counterb <= counterb-"00001"; |

130 | cinout <= '0' ; |

131 | ```
else
``` |

132 | counterb<="01010"; |

133 | countera<=dc &'0'; |

134 | next_s <= s5; |

135 | end if; |

136 | end if; |

137 | |

138 | when s5 => |

139 | |

140 | if rising_edge(clk) then |

141 | if countera /= "00000" then |

142 | countera <= countera-"00001"; |

143 | cinout <= not (cinout) ; |

144 | counterb<="01010"; |

145 | |

146 | elsif (countera = "00000") and (counterb/="00000") then |

147 | counterb <= counterb-"00001"; |

148 | cinout <= '0' ; |

149 | ```
else
``` |

150 | counterb<="01010"; |

151 | countera<=db &'0'; |

152 | next_s <= s6; |

153 | end if; |

154 | end if; |

155 | |

156 | |

157 | when s6 => |

158 | |

159 | if rising_edge(clk) then |

160 | if countera /= "00000" then |

161 | countera <= countera-"00001"; |

162 | cinout <= not (cinout) ; |

163 | counterb<="01010"; |

164 | |

165 | elsif (countera = "00000") and (counterb/="00000") then |

166 | counterb <= counterb-"00001"; |

167 | cinout <= '0' ; |

168 | ```
else
``` |

169 | counterb<="01010"; |

170 | countera<=da &'0'; |

171 | next_s <= s7; |

172 | end if; |

173 | end if; |

174 | when s7 => |

175 | |

176 | if rising_edge(clk) then |

177 | if countera /= "00000" then |

178 | countera <= countera-"00001"; |

179 | cinout<= not (cinout) ; |

180 | counterb<="01010"; |

181 | |

182 | elsif (countera = "00000") and (counterb/="00000") then |

183 | counterb <= counterb-"00001"; |

184 | cinout <= '0' ; |

185 | ```
else
``` |

186 | counterb<="01010"; |

187 | countera<=dh &'0'; |

188 | next_s <= s0; |

189 | end if; |

190 | end if; |

191 | |

192 | |

193 | end case; |

194 | end process; |

195 | |

196 | end behavioral; |