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Forum: FPGA, VHDL & Verilog how to use clk in fsm


von daniel (Guest)


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I want to build a final state machine embodies eight numbers and then 
she proceeded to tell the eighth.
For example if  the  eight number  is four I want the machine extract 
four pulses of 1 clock cycle difference between between pulses and then 
wait another 10 clock cycles and then switches to the next state( and in 
the next do the same thing).
The problem that he dosent let me use the clock in the states ..
Does anyone have an idea what to do?


The code
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.std_logic_unsigned.all;
4
use ieee.std_logic_arith.all;
5
6
entity pulsim is 
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   port( 
8
    resetN, clk : in std_logic;
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    da         : in std_logic_vector(3 downto 0) ;
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        db         : in std_logic_vector(3 downto 0) ;
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        dc         : in std_logic_vector(3 downto 0) ;
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        dd         : in std_logic_vector(3 downto 0)  ;
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        de         : in std_logic_vector(3 downto 0)  ;
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        df         : in std_logic_vector(3 downto 0)  ;
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        dg         : in std_logic_vector(3 downto 0)  ;
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        dh         : in std_logic_vector(3 downto 0)  ;
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    sinus      : out  std_logic);
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end pulsim ; 
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architecture behavioral of pulsim is 
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21
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type state_type is (s0,s1,s2,s3,s4,s5,s6,s7);
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signal current_s,next_s: state_type;
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signal countera : std_logic_vector(4 downto 0) :=dh &'0' ;
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signal counterb : std_logic_vector(4 downto 0) :="01010" ;
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signal cinout   : std_logic ;
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begin 
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process ( resetN , clk)
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   begin
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    if resetN = '0' then
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        current_s <= s0;
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  elsif (rising_edge(clk)) then
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  current_s <= next_s;
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  end if;
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   end process;
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39
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process (current_s,dh,clk)
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begin
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  sinus <= cinout ;
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  case current_s is
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     when s0 =>        --when current state is "s0"
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     if(dh ="1111") then
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      cinout <= '0';
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      next_s <= s0;
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   else
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    if clk='1' then
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      if countera /= "00000" then
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        countera <= countera-"00001";
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        cinout<= not(cinout);
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        counterb<="01010";
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      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=dg &'0';
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      next_s <= s1;
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      end if;
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    end if;
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  end if;
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  when s1 => 
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    if rising_edge(clk) then
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      if countera /= "00000" then
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        countera <= countera-"00001";
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        cinout <= not (cinout) ;
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        counterb<="01010";
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      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=df &'0';
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      next_s <= s2;
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      end if;
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    end if;        
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  when s2 => 
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    if rising_edge(clk) then
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      if countera /= "00000" then
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        countera <= countera-"00001";
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        cinout <= not (cinout) ;
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        counterb<="01010";
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      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=de &'0';
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      next_s <= s3;
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      end if;
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    end if;  
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    when s3 => 
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    if rising_edge(clk) then
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      if countera /= "00000" then
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        countera <= countera-"00001";
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        cinout <= not (cinout) ;
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        counterb<="01010";
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      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=dd &'0';
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      next_s <= s4;
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      end if;
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    end if;              
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    when s4 => 
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    if rising_edge(clk) then
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      if countera /= "00000" then
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        countera <= countera-"00001";
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        cinout <= not (cinout) ;
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        counterb<="01010";
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      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=dc &'0';
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      next_s <= s5;
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      end if;
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    end if;  
137
    
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    when s5 => 
139
    
140
    if rising_edge(clk) then
141
      if countera /= "00000" then
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        countera <= countera-"00001";
143
        cinout <= not (cinout) ;
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        counterb<="01010";
145
      
146
      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=db &'0';
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      next_s <= s6;
153
      end if;
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    end if;                  
155
    
156
    
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    when s6 => 
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    if rising_edge(clk) then
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      if countera /= "00000" then
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        countera <= countera-"00001";
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        cinout <= not (cinout) ;
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        counterb<="01010";
164
      
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      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=da &'0';
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      next_s <= s7;
172
      end if;
173
    end if;    
174
    when s7 => 
175
    
176
    if rising_edge(clk) then
177
      if countera /= "00000" then
178
        countera <= countera-"00001";
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        cinout<= not (cinout) ;
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        counterb<="01010";
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      elsif (countera = "00000") and (counterb/="00000") then
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          counterb <= counterb-"00001";
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          cinout <= '0' ;
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      else
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      counterb<="01010";
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      countera<=dh &'0';
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      next_s <= s0;
189
      end if;
190
    end if;            
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192
  
193
  end case;
194
end process;
195
196
end behavioral;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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daniel wrote:
> a final state machine
In fact its a "finite" state machine. That means: this machine only has 
a limited number of states. The opposite would be a machine with 
uncountable sates, a machine with "infinte states"...

> The problem that he dosent let me use the clock in the states ..
> Does anyone have an idea what to do?
You have a VERY, VERY strange way of using a clock. Can you show me any 
example doing it a similar way?

No?

Correct. The only way to use a clock for synthesis is at the very 
beginning of a process. And additionally you should (for beginners 
"must") have only one clock sensitive to the same edge throughout.

And now simply have a look how others did that thing with those FSM.
A hint: a "rising_edge(clk)" involves a flipflop. And that's the state 
memory.
Additionally you need some logic to calculate the next state.
That's all...


One is fairly easy to see: you did programming in C previously. And now 
you want to "program" with VHDL. But if that was a "programming 
language", then it would be VHPL...
So up to now you have the wrong way of thinking: you think in software, 
but you must think in hardware. And then you can "describe" your 
thoughts.


BTW: did you see the "formatting options" for VHDL code a few lines 
above the text edit box? Use it. Its magic...

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Initialization with a non constant values is NOT synthesizeable (the 
init value can't be predicted by the synthesizer!!!):
1
signal countera : std_logic_vector(4 downto 0) :=dh &'0' ;


Now lets have a second look at your code. And there its easy to see the 
usual beginners problems with the 2-process-FSM: you have a 
combinatorial process and a process for the flipflops. But when you want 
to count, then that counter itself is (the simplest way of) a FSM. And 
each FSM has: flipflops and logic. And as that counter is an FSM also, 
it must have flipflops and logic.
As i said previously you will get flipflops when you use a 
"rising_edge()" (or a "falling_edge()" or a "'event"). Yo tried to 
involve that into your combinatorial process, and now you have two 
processes generating flipflops. Thats not the intention of writing a 
2-process-FSM.

What to do now?
1. use the 2-process-FSM further on.
Then you will have to kick out the clk of the combiunatorial process, 
and to invoke some signals like countera_next and counterb_next. And you 
will have to calculate the "next" value in the combinatorial process and 
you will have to transfer the "next" counter values to countera and 
counterb in the clocked process.

2. use the 1-process-FSM.
Then you will have to kich off those "next" values and you will have to 
invoke the clock to the combinatorial process.

Heres your problem analyzed:
http://www.lothar-miller.de/s9y/archives/43-Ein-oder-Zwei-Prozess-Schreibweise-fuer-FSM.html
Try it with Google translator, its German...

As a result it will look this way as a 1-process-FSM:
1
type state_type is (s0,s1,s2,s3,s4,s5,s6,s7);
2
signal state: state_type;
3
4
signal countera : std_logic_vector(4 downto 0) :="00000" ;
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signal counterb : std_logic_vector(4 downto 0) :="01010" ;
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signal cinout   : std_logic ;
7
8
begin 
9
   
10
sinus <= cinout ;
11
12
process (clk)
13
begin
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  if (rising_edge(clk)) then  -- the one and only clock
15
16
   case state is
17
   when s0 =>        --when current state is "s0"
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     if(dh ="1111") then
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      cinout <= '0';
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      next_s <= s0;
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     else
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      if countera /= "00000" then
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        countera <= countera-"00001";
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        cinout<= not(cinout);
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        counterb<="01010";
26
      
27
      elsif (countera = "00000") and (counterb/="00000") then
28
          counterb <= counterb-"00001";
29
          cinout <= '0' ;
30
      else
31
      counterb<="01010";
32
      countera<=dg &'0';
33
      next <= s1;
34
      end if;
35
     end if;
36
37
   when s1 => 
38
      if countera /= "00000" then
39
        countera <= countera-"00001";
40
        cinout <= not (cinout) ;
41
        counterb<="01010";
42
      
43
      elsif (countera = "00000") and (counterb/="00000") then
44
          counterb <= counterb-"00001";
45
          cinout <= '0' ;
46
      else
47
        counterb<="01010";
48
        countera<=df &'0';
49
        next <= s2;
50
      end if;
51
    
52
    :      
53
    :      
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55
    when s7 => 
56
      if countera /= "00000" then
57
        countera <= countera-"00001";
58
        cinout<= not (cinout) ;
59
        counterb<="01010";
60
      
61
      elsif (countera = "00000") and (counterb/="00000") then
62
          counterb <= counterb-"00001";
63
          cinout <= '0' ;
64
      else
65
        counterb<="01010";
66
        countera<=dh &'0';
67
        next_s <= s0;
68
      end if;
69
  
70
    end case;
71
  end if; -- the one and only clock
72
end process;
73
74
end behavioral;

BTW: I strongly recommend to use the numeric_std lib instead of that old 
Synopsis libs...
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std
I also strongly recommend using integers for counting. Its FAR WAY 
easier to read this here:
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
use IEEE.NUMERIC_STD.ALL;
4
:
5
:
6
signal countera : integer range 0 to 10 := 0;
7
signal counterb : integer range 0 to 10 := 10;
8
:
9
    when s7 => 
10
      if countera /= 0 then
11
        countera <= countera-1;
12
        cinout   <= not (cinout) ;
13
        counterb <= 10;
14
      elsif (countera = 0 and (counterb /= 0) then
15
        counterb <= counterb-1;
16
        cinout   <= '0' ;
17
      else
18
        counterb <= 10;
19
        countera <= to_integer(unsigned(dh))*2;
20
        next_s   <= s0;
21
      end if;
22
:
23
:
And as you see I also strongly recommend to use indetion to get an 
easily readable code...

: Edited by Moderator

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