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Forum: FPGA, VHDL & Verilog VHDL calculator matrix input help.


VHDL calculator matrix input help.
von ed jones (Guest)

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code for matrix button input so far. getting signals from buttons but 
not sending signals to 4bit led output,
any help would be great.

1
Library IEEE;

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Use IEEE.STD_LOGIC_1164.ALL;

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Use IEEE.STD_LOGIC_ARITH.ALL;

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Use IEEE.STD_LOGIC_UNSIGNED.ALL;

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Entity keypad_input is

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Port( clk                : in std_logic;

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      col_line           : in  std_logic_vector(2 downto 0);

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      row_line           : out std_logic_vector(3 downto 0);

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      Number             : out std_logic_vector(3 downto 0));

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End keypad_input;

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Architecture Behavior of keypad_input is 

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signal sig_c : std_logic_vector(2 downto 0):= "000";

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signal sig_r : std_logic_vector(3 downto 0):= "0001" ;

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signal num  : std_logic_VECTOR (3 DOWNTO 0);

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Signal C0    : std_logic_vector (2 downto 0):= "000";

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Signal C1    : std_logic_vector (2 downto 0):= "000";

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Signal C2    : std_logic_vector (2 downto 0):= "000";

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begin

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-- send signal to rows of keypad --

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process (clk) is

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  Begin

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    If (clk 'event and clk = '0') then

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  sig_r <= sig_r(0) & sig_r(3 downto 1);        

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end if;

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end process;

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 row_line <= sig_r;

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debounce: process (clk,sig_c,col_line) is

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  Begin

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    If (Clk 'event and Clk = '1') then

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       C0 <= C0(1 downto 0) & Col_line(0);

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       C1 <= C1(1 downto 0) & Col_line(1); 

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       C2 <= C2(1 downto 0) & Col_line(2);

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    end if;

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sig_c(0) <= C0(0) and C0(1) and (not C0(2));

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sig_c(1) <= C1(0) and C1(1) and (not C1(2));

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sig_c(2) <= C2(0) and C2(1) and (not C2(2));

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 End process;

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-- read debounces signals --

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input: Process (num, sig_r, sig_c)  is

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begin

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if sig_r = "0001" then

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  if sig_c(0) = '1' then 

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    num <= "1110"; -- e

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  elsif sig_c(1) = '1' then

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    num <= "0000"; -- 0

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  elsif sig_c (2) = '1' then 

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    num <= "1010"; -- a

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   else null;

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  end if;

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elsif sig_r = "0010" then

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  if sig_c(0) = '1' then 

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    num <= "0011"; -- 3

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  elsif sig_c(1) = '1' then

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    num <= "0010"; -- 2

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  elsif sig_c (2) = '1' then  

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    num <= "0001"; -- 1

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  else null;

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  end if;

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elsif sig_r = "0100" then

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  if sig_c(0) = '1' then 

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    num <= "0110"; -- 6

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  elsif sig_c(1) = '1' then

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    num <= "0101"; -- 5

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  elsif sig_c (2) = '1' then  

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    num <= "0100"; -- 4

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  else null;

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  end if;

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elsif sig_r = "1000" then

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  if sig_c(0) = '1' then 

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    num <= "1001"; -- 9

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  elsif sig_c(1) = '1' then

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    num <= "1000"; -- 8

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  elsif sig_c (2) = '1' then 

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    num <= "0111"; -- 7

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  else null;

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  end if;

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 end if;  

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end process;

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number <= num;

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end Behavior;


  


  



  

  
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    Re: VHDL calculator matrix input help.
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

      

      

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ed jones wrote:
> getting signals from buttons but not sending signals to 4bit led output
How did you find that out? What do you expect? And what do you get 
instead?


BTW1: your "debounce" process suffers three big design flaws.
1. sig_c and col_line are not necessary in the sensitivity list.
2. at the moment C0, C1 and C2 are missing for a correct simualation!!
3. do NOT combine synchronous and combinatorial processes into one.
So finally: only clk must be in that sensitivity list. And after 
"end if" there must follow "end process":
1
  process (clk) begin

2
    If (Clk 'event and Clk = '1') then

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       -- this is the synchronous process

4
    end if;

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    -- nothing here!!!!!!!

6
  end process;



BTW2: please read that very short manual for the editbox here. Most 
important is that thing with those [vhdl] tags...

  


  



  

  
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