Forum: FPGA, VHDL & Verilog VHDl for a custom CLB

von Johnny (Guest)

Attached files:

Rate this post
0 useful
not useful

Can someone help me in understanding, how to write a VHDL model for the 
schematic proposed in the figure? Any suggestions, ideas or smart tools 
are really appreciated.



Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.