Hi members, I have 4 different memories of same depth and width. so i have a write logic with which i can select memory with 2 bit control signal.. also I am generating address signals depending on my memory selection. problem: i can write to next memory only when i complete writing all memory locations of 1st memory...i.e i should sample my next control signal only when i finish all memory locations of first memory eg:if control signal is 00 memory1 is selected and my address counter starts counting from 000 to 111 (data also sent in parellel)...once complete....then sample next control signal for writing memory2...
felix89 wrote: > problem: ... Major problem for an answer is: unknown code and unknown target. But as far as I see, theres no answer necessary because there's no question... :-o
port(ctrl:in std_logic_vector(1 downto 0);
addr:out std_logic_vector(2 downto 0));
architecture
addr1, addr2,addr3,addr4:std_logic_vector(2 downto 0);
begin
process(clk,rst)
....
....
case(ctrl)
when 00 =>addr <= var1;
var1<=var1+1:
when 01 =>addr <= var2;
var2<=var2+1:
when 10 =>addr <= var3;
var3<=var3+1:
when 11 =>addr <= var4;
var4<=var1+4:
end case
end process;
here address is generated for four different memories depending on ctrl
signal...question is i need a logic such that ill sample the next
control signal only when all addresses for previous control signal is
generated....ie if i select ctrl to be 00 then addr counts from 000 to
111
even if ctrl changes in between it does not matter..
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