Forum: FPGA, VHDL & Verilog DCT code. Don't know why it is not working.

von Ajay Mittal (Guest)

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One file is vhdl code another is testbench code.
It is program for DCT(Discrete cosine transform).
Assumed to take eight 16 bit inputs in first 8 clock cycles and in the 
coming 8 cycles eight 16 bit output y will come.
but at present no output is coming.
Please neglect logical mistakes. Only help me with syntax or other 
Its urgent so please help me out guys.

von adelheit (Guest)

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I see only your testbench.

You can make your coad also visible with some tags.
VHDL code

von Lothar M. (lkmiller) (Moderator)

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adelheit wrote:
> I see only your testbench.
2 times the same? And not much in it...

> I see only your testbench.
And pls attach *.vhd or *.vhdl files!
Not *.txt files.
Then you will see some kind of magic named "syntax highlighting"...


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