One file is vhdl code another is testbench code. It is program for DCT(Discrete cosine transform). Assumed to take eight 16 bit inputs in first 8 clock cycles and in the coming 8 cycles eight 16 bit output y will come. but at present no output is coming. Please neglect logical mistakes. Only help me with syntax or other mistakes. Its urgent so please help me out guys.
I see only your testbench. You can make your coad also visible with some tags.
adelheit wrote: > I see only your testbench. 2 times the same? And not much in it... > I see only your testbench. And pls attach *.vhd or *.vhdl files! Not *.txt files. Then you will see some kind of magic named "syntax highlighting"...