EmbDev.net

Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
non-nullable Dmitriy Kraftig 3
Top module problems.. John Mayer 4
Beginner problems Syntax error John Mayer 2
for loop with real angelo 3
finding square root of integer in vhdl moha 1
5 cameras in one fpga help Mark Jomari 4
Trying to divide 100Mhz clock to 25Mhz for VGA Darren Rodriguez 8
find the max value between a given inputs tamara 2
what can i do? tanko 6
the Quotient is floating point ddden 7
for loop generate find a good syntax. Olivier D. 0
ps2 interface with fpga ahmed 3
Hot FPGA REASONS Rashmi Imhsar 1
error: * can not have such operands in this context Mariem Makni 1
State Machines for an equation Hassan Mahmood 0
solution for large memory requirement for FPGA Vinayak S. 1
quick response: please help me to clear the warnings Padma Baskaran 20
use the output from counter basma hassan 11
How to include deadtime in pwm generator Tosin Akin 6
time duration for every key in keyboard ahmedhassan 9
Verilog module Need help designing a circuit 4
division on the last outputs Basma Hassan 7
Microblaze documentation Abdallah      0
design works on fpga, but in simulation a counter is always 'x' Jay Christnach 3
query on verilog code pushpalatha Gowda 4
custom processor on FPGA Lovish Jain 1
writting code in vhdl basma 9
online receive bmp tp fpga Abdallah      6
How to use Memory Abdallah      3
Pre-synthesis and post-synthesis Simulation not matched! Nisarg Shah 29
read data from file Abdallah      6
problem in vhdl code agathepower 9
How to increases Maximum operating freqency Vinayak S. 3
GTP Transciever Alexander Lutovid 3
check lsb in vhdl basma 1
sorter in vhdl basma 1
Error in Post-synthesis, ModelSim Vinayak S. 1
vhdl code to find max value from input basma 10
Need help with reading from file Miller Jackson 3
how to implement interleaver in FPGA Vinayak S. 8
dividing clock Bilel 13
state machine in vhdl Basma Hassan 20
Single Entity - Multiple architectures SM 1
Not synthesizing Vinayak S. 21
limitation memory of the FPGA Vinayak S. 1
FPGA F.M Radio Milruwan Perera 36
Implementation of DVB-T2 in VHDL Vinayak S. 5
Signal cannot be synthesized Marko Adžić 1
Logic question Sudhakar Pall 11
RAM not working as needed in spartan 3 vhdl newbie 2
Need help with VHDL reading from file Darren Seow 2