I have an ax8 from opencores that runs a counter that shows on the leds on my development board. I'm very happy, it works. I wanted to simulate this too, after all this is very educational. I also wanted to change the program with a generated rom in block ram afterwards. I wrote a very simple text fixture in Verilog (the ax8 is in VHDL) to run my simulation. Unfortunately the counter clk_div stays undefined all the time, so the processor doesn't even get its clock to work. I use Xilinx webpack 12.4 and ISim for this. I attached the top-level module and the test-fixture code to this post. What am I doing wrong? Many thanks in advance.
Jay Christnach wrote: > Unfortunately the counter clk_div stays undefined all the time Give it an initial value: signal clk_div : std_logic_vector(15 downto 0) := (others=>'0'); This may also apply to the other signals... BTW: in my eyes this design is rubbish! Never ever generate a clock like this:
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The FPGA designer implemented clock managers to generate clocks.
Hello Lothar, Many thanks. This did help indeed. I'm impressed by the enormous verbosity of VHDL. I still have to learn this, for now I'm still Verilog only. But how do I know if I have to set an initial value like this? In the whole rest of the design I didn't have to change anything, but it all worked. I copied the top level from an experienced developer, the rest is the ax8 from opencores. Maybe you want to explain what I would gain from a DCM, but I guess I can look that up elsewhere. After all this works independantly from the tools or hardware. It's maybe a quick and dirty way to do it. BTW, I also came across your website, which has a lot of information. Thanks again! Jay
Jay Christnach wrote: > Many thanks. You're welcome. > But how do I know if I have to set an initial value like this? You can/should/must set ist for registered values (those being clocked) if you don't have a explicit reset path in the process (which is usuallay not necessary, see WP272 from Xilinx). You just must know, that the simulator inititlizes signals/variables implcitly with the leftmost value of the according type if you don't explicitly assign your desired value. And the leftmost value for the type std_logic is 'U' (http://www.quicknet.se/hdc/hdl/educaton/types/exampl.htm) which results together with something else to an 'X'. The synthesizer is not able to do anything other than '1' and '0' inside the FPGA (and also a 'Z' on the IO cells), and so it assigns a '0' to uninitialized values. Therefore often the rumor is: in real life it is ok, in simulation it doesn't work! And thats only a hint that the simulation is simply wrong due to an incomplete VHDL model. In Verilog lots of those declarations are implicitly done and a little bit more hidden from an occasional reader. VHDL is more straightforward, you must explicitly write down such things and so it is more obvious that/when they are missing.