I generated a fifo buffer using IP core, and are now having problem
using it.
I made This is my top module
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | entity top is
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4 | Port (
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5 | Mclk: in std_logic;
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6 | LED : out STD_LOGIC_VECTOR (5 downto 0);
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7 | LEDf: out std_logic;
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8 | LEDE: out std_logic;
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9 | BTN : in STD_LOGIC_VECTOR (3 downto 0);
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10 | Switch : in STD_LOGIC_VECTOR (7 downto 0));
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11 | end top;
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12 | architecture Behavioral of top is
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13 |
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14 | Component FIFO IS
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15 | PORT (
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16 | clk : IN STD_LOGIC;
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17 | rst : IN STD_LOGIC;
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18 | din : IN STD_LOGIC_VECTOR(98 DOWNTO 0);
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19 | wr_en : IN STD_LOGIC;
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20 | rd_en : IN STD_LOGIC;
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21 | dout : OUT STD_LOGIC_VECTOR(98 DOWNTO 0);
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22 | full : OUT STD_LOGIC;
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23 | empty : OUT STD_LOGIC
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24 | );
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25 | END component;
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26 | begin
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27 | process(Mclk)
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28 | begin
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29 | if rising_edge(mclk) then
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30 | clk <= mclk;
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31 | LEDf <= full;
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32 | LEDe <= empty;
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33 | wr_en<= BTN(0);
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34 | rd_en<= BTN(1);
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35 | rst <= BTN(2);
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36 | din <= switch;
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37 | dout <= LED;
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38 | end if;
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39 | end process;
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40 | end Behavioral;
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why isn't this working, it isn't recognizing the input ports on my
fifo.. these are the error messages.
1 | Line 59. Undefined symbol 'clk'.
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2 | Line 60. Undefined symbol 'full'. Should it be: null?
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3 | Line 60. full: Undefined symbol (last report in this block)
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4 | Line 61. Undefined symbol 'empty'.
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5 | Line 61. empty: Undefined symbol (last report in this block)
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6 | Line 62. Undefined symbol 'wr_en'.
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7 | Line 63. Undefined symbol 'rd_en'.
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8 | Line 64. Undefined symbol 'rst'.
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9 | Line 65. Undefined symbol 'din'. Should it be: in or min?
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10 | Line 66. Undefined symbol 'dout'. Should it be: out?
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