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Top module problems..
von John M. (215)

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I generated a fifo buffer using IP core, and are now having problem 
using it.

I made This is my top module

1
library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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entity top is

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    Port ( 

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        Mclk:  in std_logic;

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        LED : out  STD_LOGIC_VECTOR (5 downto 0);

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        LEDf: out std_logic;

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        LEDE: out std_logic;

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           BTN : in  STD_LOGIC_VECTOR (3 downto 0);

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           Switch : in  STD_LOGIC_VECTOR (7 downto 0));

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end top;

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architecture Behavioral of top is

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Component FIFO IS

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  PORT (

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    clk : IN STD_LOGIC;

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    rst : IN STD_LOGIC;

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    din : IN STD_LOGIC_VECTOR(98 DOWNTO 0);

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    wr_en : IN STD_LOGIC;

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    rd_en : IN STD_LOGIC;

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    dout : OUT STD_LOGIC_VECTOR(98 DOWNTO 0);

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    full : OUT STD_LOGIC;

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    empty : OUT STD_LOGIC

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  );

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END component;

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begin

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process(Mclk)

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begin

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if rising_edge(mclk) then 

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  clk <= mclk;

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  LEDf <= full; 

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  LEDe <= empty; 

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  wr_en<= BTN(0); 

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  rd_en<= BTN(1);

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  rst <= BTN(2); 

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  din <= switch;

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  dout <= LED;

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end if;

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end process;

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end Behavioral;


why isn't this working, it isn't recognizing the input ports on my 
fifo.. these are the error messages.

1
Line 59. Undefined symbol 'clk'.

2
Line 60. Undefined symbol 'full'.  Should it be: null?

3
Line 60. full: Undefined symbol (last report in this block)

4
Line 61. Undefined symbol 'empty'.

5
Line 61. empty: Undefined symbol (last report in this block)

6
Line 62. Undefined symbol 'wr_en'.

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Line 63. Undefined symbol 'rd_en'.

8
Line 64. Undefined symbol 'rst'.

9
Line 65. Undefined symbol 'din'.  Should it be: in or min?

10
Line 66. Undefined symbol 'dout'.  Should it be: out?


  


  




  

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    Re: Top module problems..
  


  

    

      von
      
        Clem (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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It doesn't know any or your ports (not just your input).
You have to instantiate your FIFO.
Have a look at a easy port map example.
e.g. 
https://www.doulos.com/knowhow/vhdl_designers_guide/components_and_port_maps/

  


  




  

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    Re: Top module problems..
  


  

    

      von
      
        John M.
        (215)
        
      
      


      
    


    

      
    

    

    

  
  


  

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I am not quite sure on how i should instantiate a component?
isn't what iam doing with component in my arcitecture?

-- EDIT--
1
entity top is

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    Port ( 

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        Mclk:  in std_logic;

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        LED : out  STD_LOGIC_VECTOR (5 downto 0);

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        LEDf: out std_logic;

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        LEDE: out std_logic;

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           BTN : in  STD_LOGIC_VECTOR (3 downto 0);

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           Switch : in  STD_LOGIC_VECTOR (7 downto 0));

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end top;

10
architecture Behavioral of top is

11
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Component FIFO IS

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  PORT (

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    clk : IN STD_LOGIC;

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    rst : IN STD_LOGIC;

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    din : IN STD_LOGIC_VECTOR(98 DOWNTO 0);

17
    wr_en : IN STD_LOGIC;

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    rd_en : IN STD_LOGIC;

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    dout : OUT STD_LOGIC_VECTOR(98 DOWNTO 0);

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    full : OUT STD_LOGIC;

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    empty : OUT STD_LOGIC

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  );

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END component;

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begin

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G1: FIFO Port map (clk <= mclk , LEDf <= full, LEDe <= empty, wr_en<= BTN(0), rd_en<= BTN(1),rst <= BTN(2),din <= switch,dout <= LED); 

27
end Behavioral;


Errors:
1
Line 57. Undefined symbol 'clk'.

2
Line 57. clk: Undefined symbol (last report in this block)

3
Line 57. Undefined symbol 'full'.  Should it be: null?

4
Line 57. full: Undefined symbol (last report in this block)

5
Line 57. Undefined symbol 'empty'.

6
Line 57. empty: Undefined symbol (last report in this block)

7
Line 57. Undefined symbol 'wr_en'.

8
Line 57. wr_en: Undefined symbol (last report in this block)

9
Line 57. Undefined symbol 'rd_en'.

10
Line 57. rd_en: Undefined symbol (last report in this block)

11
Line 57. Undefined symbol 'rst'.

12
Line 57. rst: Undefined symbol (last report in this block)

13
Line 57. Undefined symbol 'din'.  Should it be: in or min?

14
Line 57. din: Undefined symbol (last report in this block)

15
Line 57. Undefined symbol 'dout'.  Should it be: out?

16
Line 57. dout: Undefined symbol (last report in this block)

17
Line 57. IN mode Formal clk of FIFO with no default value must be associated with an actual value.


  


  



  

  
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    Re: Top module problems..
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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How does this fifo look like? Is there a entity "fifo"?

  


  




  

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    Re: Top module problems..
  


  

    

      von
      
        John M.
        (215)
        
      
      


      
    


    

      
    

    

    

      

      

      Attached files:


      

    

  
  


  

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Not in my Top module, but i have a VHDL module called Fifo, which is 
generated by using the IP core

The FIFO vhd file is attached.

  


  




  

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