Hello Verilog Experts,
I am looking to optimize my code in terms of gates/logic. Please
suggest.
I have a 64 bit wide 512 elements array
module A;
reg [63:0] data [511:0]
...
endmodule
Each data array element is mapped to a signal internal to the design.
Now, I need to send ONLY the array elements that changed in current
clock cycle through to some external pins.
Think of it all in FPGA Hardware.
To detect which element changed, I could copy the whole arrray into
some local 64 bit 512 array in previous clock cycle, xor with the
current clock array element etc... but this would eat up a lot of
register space, increase step count and all ... Is there a better way to
identify which of the array elements changed in current clock cycle
(compared to the previous). Thanks.
PS: I am interested in every array element but not in each bit.
Sudhakar Pall wrote: > Is there a better way to identify which of the array elements changed > in current clock cycle (compared to the previous). If you get the data in parallel and you want to do all of the compare procedure in one clock cycle, then it will need at least 64*512 = 32768 flipflops. Theres no chance to escape. But if you get the data via a serial interface you could compare it in small amounts step by step. So the questions are: WHERE does this data come from? WHERE does it go to? WHAT data rates do you need?
Lothar Miller wrote: > Sudhakar Pall wrote: >> Is there a better way to identify which of the array elements changed >> in current clock cycle (compared to the previous). > If you get the data in parallel and you want to do all of the compare > procedure in one clock cycle, then it will need at least 64*512 = > 32768 flipflops. Theres no chance to escape. > > But if you get the data via a serial interface you could compare it in > small amounts step by step. > > So the questions are: WHERE does this data come from? WHERE does it go > to? WHAT data rates do you need? Data is in parallel and goes out through external pins. FPGA connected to a target interface, design is on the FPGA (includes this module as well) and I would like to minimize the data going out through to the target connected. I am ignorant to the data rates for now since much of it depends on target interface connected. Here is what I was thinking, please let me know if you think of better ways, Prototype: reg [63:0] data [511:0] reg [63:0] prev_clock_data[511:0] reg transition [511:0] transition [i] = | (prev_clock_data.. ^ data.. ) for loop ... if (transition [i] ) external_interface = data [i]; I am trying to look and see if I could optimize the number of registers used here. How to store previous clock data running by the same clock on FPGA is another thing, suggestions would help me here too. Thanks.
Sudhakar Pall wrote: > reg [63:0] data [511:0] > Data is in parallel 512 pins for data input, really? > for loop ... Did you know: each loop in Verilog/VHDL is unrolled to real parallel hardware.
Lothar Miller wrote: > Sudhakar Pall wrote: >> reg [63:0] data [511:0] >> Data is in parallel > 512 pins for data input, really? Data bus included module is within the FPGA. No external /IO. > >> for loop ... > Did you know: each loop in Verilog/VHDL is unrolled to real parallel > hardware. I am missing your point here. Can you elaborate ?
Sudhakar Pall wrote: > Lothar Miller wrote: >> Sudhakar Pall wrote: >>> reg [63:0] data [511:0] >>> Data is in parallel >> 512 pins for data input, really? > > Data bus included module is within the FPGA. No external /IO. > >> >>> for loop ... >> Did you know: each loop in Verilog/VHDL is unrolled to real parallel >> hardware. > > I am missing your point here. Can you elaborate ? I mean I understand the fact how hardware / FPGA handles the logic, but don't quite get where you are heading with this.
Sudhakar Pall wrote: > Data bus included module is within the FPGA. No external /IO. So: where does the data come from? Sudhakar Pall wrote: > but don't quite get where you are heading If the data is generated one data line after the other, then it is not necessary to compare the whole array every clock cycle. Instead it would be enough to compare only line...
Perhaps you can put a 64-Bit Comparator between the Signal Source and the Data lines of RAM-block where the Signal will be stored. When the Comparator has detected a difference the FPGA should save the address lines of that RAM Cell or set a '1' in an 510Bit Array that represent the Position of the Difference.
Uwe wrote: > the Data lines of RAM-block where the Signal will be stored With the description above no RAM will be invoked. The design also will not be mapped into LUTs, insted each of the 32768 memory bits will eat up one flipflop.
> Each data array element is mapped to a signal internal to the design.
oh, I missed it ...
Lothar Miller wrote: > Sudhakar Pall wrote: >> Data bus included module is within the FPGA. No external /IO. > So: where does the data come from? Design is synthesized on FPGA's. There are 64 bit signals from the core logic that are assigned to data array elements. Probably I could have data as wire, use local_data to store up for previous clock cycles data and then perform xor operation on both to detect the transition. This atleast makes things a bit more clear, thanks for asking the question. > > Sudhakar Pall wrote: >> but don't quite get where you are heading > If the data is generated one data line after the other, then it is not > necessary to compare the whole array every clock cycle. Instead it > would be enough to compare only line... But I will have to save previous data into register ... so that many flops. I guess that cannot avoided.
Sudhakar Pall wrote: > But I will have to save previous data into register ... But as far as I see previous Data is only 64 bits wide. Thats much less than 32768...
Watch this topic
Disable multi-page viewPlease log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.