RAM not working as needed in spartan 3

vhdl n. OP (Company: none) #3497615
Rate this post
• ▲ useful
▼ not useful 
hi guys,

       i've used this code as a ram block in Spartan 3. But it was not 
working.
i checked the RTL view of the file, but in that the RAM block have 2 
pins unassigned(ENA and RSTA).

is that the problem why this is not working?

also the RAM created is a dual port RAM. I need only a single port RAM.

please help.

thanks in advance.
Attached files:
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Lothar M. Moderator (Company: Titel) #3497655
Rate this post
• ▲ useful
▼ not useful 
vhdl newbie wrote:
>         data_o <= "ZZZZZZZZ";
This is not possible inside a FPGA. There are no tristate lines in 
FPGAs anymore.

> i've used this code as a ram block in Spartan 3.
Where did you take it from? Did you check out the templates Xilinx 
delivers with the ISE? And did you check the XST User Guide? In there 
you can find how to describe a RAM so that the synthesizer can recognize 
it correctly...
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.