Forum: FPGA, VHDL & Verilog sorter in vhdl

von basma (Guest)

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Hi All;
i want to design vhdl code for sorter.
the idea for the sorter is as the following
i have input data which is std_logic vector(0 to 7) and every input has 
its time i.e if i have input 010111001 its time is 20 ns ....etc
and i want to sort every input according its time
how i can make it in vhdl code.every-help will e thankful for it

von Alexander F. (alexf91)

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I'm not sure what you mean when you say "every input has it's time", but 
this will probably help you:


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