# Forum: FPGA, VHDL & Verilog writting code in vhdl

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hi all,,,
i want a code in vhdl to make this equation . like the the following
d(s1,s2)=(1+1+0+1+1)/(n^2/2)=4/12=0.33333 .
(1+1+0+1+1) is the distances between input data use the accumulator to
sum the distances.
n is the number of input data if even multiply n*n if odd n*n-1
then divide accumulator over the numbers of inputs if even or odd
i want a help please in how to make this vhdl code

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1. Show us, what have you done so far.
2. Ask particular questions.

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Duke Scarring wrote:
> 1. Show us, what have you done so far.

ok
how i make it in vhdl code
d(s1,s2)=(1+1+0+1+1)/(n^2/2)=4/12=0.33333 .

 library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.std_logic_1164.all; entity test is port( rst : in std_logic; clk : in std_logic; we : in std_logic; wr_data1 : in std_logic_vector(7 downto 0); wr_data2 : in std_logic_vector(7 downto 0); wr_addr : in integer range 0 to 255; N_of_samp: out integer range 0 to 255; distance : out integer range 0 to 255; sum : out integer range 0 to 255; vout : out std_logic; no_match : out std_logic ); end entity; signal accum : integer range 0 to 255 := 0; signal dis : integer range 0 to 255 := 0; signal n : integer range 0 to 255 := 0; process (n,accum) begin if (n mod 2) /= 0 then N_of_samp <= (n*n)-1; else N_of_samp <= (n*n); end if; end process; end rtl; 

i try to do it in a part of the code but it calculate n
like(1,2,3,....10)
and test it if even make n*n and if odd make n*n-1
and i want to use the result oonoly i.e i want t use the result of
conter 10 and test it then make division but it gave me result like the
picture attached.
i hope y understand me

: Edited by Moderator

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Where does n came from?
In you code it is always zero.

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The posted code does not match the screenshot.

Pls. add the tokens [ vhdl ] and [ /vhdl ] without the blanks around
your VHDL code. This will give you neat syntax highlighting...

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n came from a counter count the number of input samples
 library ieee; use ieee.std_logic_1164.all; entity test is port( rst : in std_logic; clk : in std_logic; we : in std_logic; wr_data1 : in std_logic_vector(7 downto 0); wr_data2 : in std_logic_vector(7 downto 0); wr_addr : in integer range 0 to 255; distance : out integer range 0 to 255; norm_distance:out integer range 0 to 255; sum : out integer range 0 to 255; vout : out std_logic; no_match : out std_logic ); end entity; architecture rtl of test is signal rd_data1 : std_logic_vector(7 downto 0); signal rd_data2 : std_logic_vector(7 downto 0); signal rd_addr1 : integer range 0 to 255 := 0; signal rd_addr2 : integer range 0 to 255 := 0; signal accum : integer range 0 to 255 := 0; signal dis : integer range 0 to 255 := 0; signal norm_dis : integer range 0 to 255 := 0; signal n : integer range 0 to 255 := 0; signal n_of_samples : integer range 0 to 255 := 0; type states is (s0,s1,s2); signal state: states; component wr_rd_ram port( clk : in std_logic; we : in std_logic; wr_data : in std_logic_vector(7 downto 0); wr_addr : in integer range 0 to 255; rd_addr : in integer range 0 to 255; rd_data : out std_logic_vector(7 downto 0) ); end component; begin ram1:entity work.wr_rd_ram port map( clk => clk, we => we, wr_data => wr_data1, wr_addr => wr_addr, rd_addr => rd_addr1, rd_data => rd_data1 ); ram2:entity work.wr_rd_ram port map( clk => clk, we => we, wr_data => wr_data2, wr_addr => wr_addr, rd_addr => rd_addr2, rd_data => rd_data2 ); process(rst,clk) begin if rst = '1' then rd_addr1 <= 0; rd_addr2 <= 0; accum <= 0; N <= 0; state <= s0; vout <= '0'; no_match <= '0'; distance <= 0; elsif rising_edge(clk) then if we = '0' then vout <= '0'; no_match <= '0'; state <= s2; case state is when s0 => rd_addr2 <= rd_addr2 + 1; if rd_data2 = rd_data1 then N <= N + 1 ; state <= s1; dis <= abs (rd_addr1 - rd_addr2); accum <= accum + dis; vout <= '1'; elsif rd_addr2 = 255 then rd_addr2 <= 0; state <= s2; end if; when s1 => rd_addr1 <= rd_addr1 + 1; rd_addr2 <= 0; state <= s0; when s2 => no_match <= '1'; vout <= '0' ; state <= s0; when others => null; end case; end if; end if; distance <= dis ; sum <= accum ; end process; process (n,accum) begin if (n mod 2) /= 0 then N_of_samples <= (n*n)-1; norm_dist <= dis / N_of_samples; else N_of_samples <= (n*n); norm_dis <= dis / N_of_samples; end if; norm_distance <= norm_dis; end process; 
also it gave me error divide by zero

: Edited by Moderator

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basma wrote:
> if rst = '1' then
>    N     <= 0;
> ...
> if (n mod 2) /= 0 then
>    ...
> else
>    N_of_samples <= (n*n);
>    norm_dis <= dis / N_of_samples;
> end if;
>
> also it gave me error divide by zero
Just start thinking: what will happen if if reset is asserted? What is
0*0?

BTW: add the [] around  vhdl  and  /vhdl
So it looks like [/vhdl] after the end and [vhdl] before the beginning
of the VHDL code.

: Edited by Moderator

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After changing 'norm_dist' to 'norm_dis', and add a missing 'end

Did you have a testbench?

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Duke Scarring wrote:
> After changing 'norm_dist' to 'norm_dis', and add a missing 'end
>
> Did you have a testbench?

sorry for missing it ,but also if i did it gave me error divid by zero

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> Just start thinking: what will happen if if reset is asserted? What is
> 0*0?
all i want i have a counter count the number of input sample i want to
fatch the result from this counter to test it ,because it gave me
values(0,1,2....100)i want to test if 100 is even oe odd and divide
distance on it. but how i can make it

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