# Forum: FPGA, VHDL & Verilog writting code in vhdl

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hi all,,,
i want a code in vhdl to make this equation . like the the following
d(s1,s2)=(1+1+0+1+1)/(n^2/2)=4/12=0.33333 .
(1+1+0+1+1) is the distances between input data use the accumulator to
sum the distances.
n is the number of input data if even multiply n*n if odd n*n-1
then divide accumulator over the numbers of inputs if even or odd
i want a help please in how to make this vhdl code

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1. Show us, what have you done so far.
2. Ask particular questions.

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Duke Scarring wrote:
> 1. Show us, what have you done so far.

ok
how i make it in vhdl code
d(s1,s2)=(1+1+0+1+1)/(n^2/2)=4/12=0.33333 .

 1 library ieee;  2 use ieee.std_logic_1164.all;  3 library ieee;  4 use ieee.std_logic_1164.all;  5 6 entity test is  7  port(  8  rst : in std_logic;  9  clk : in std_logic;  10  we : in std_logic;  11  wr_data1 : in std_logic_vector(7 downto 0);  12  wr_data2 : in std_logic_vector(7 downto 0);  13  wr_addr : in integer range 0 to 255;  14  N_of_samp: out integer range 0 to 255;  15  distance : out integer range 0 to 255;  16  sum : out integer range 0 to 255;  17  vout : out std_logic;  18  no_match : out std_logic  19  );  20 end entity;  21 signal accum : integer range 0 to 255 := 0;  22 signal dis : integer range 0 to 255 := 0;  23 signal n : integer range 0 to 255 := 0;  24 process (n,accum)  25 begin  26 if (n mod 2) /= 0 then  27 N_of_samp <= (n*n)-1;  28 else  29 N_of_samp <= (n*n);  30 end if;  31 32 end process;  33 end rtl; 

i try to do it in a part of the code but it calculate n
like(1,2,3,....10)
and test it if even make n*n and if odd make n*n-1
and i want to use the result oonoly i.e i want t use the result of
conter 10 and test it then make division but it gave me result like the
picture attached.
i hope y understand me

: Edited by Moderator

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Where does n came from?
In you code it is always zero.

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The posted code does not match the screenshot.

Pls. add the tokens [ vhdl ] and [ /vhdl ] without the blanks around
your VHDL code. This will give you neat syntax highlighting...

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n came from a counter count the number of input samples
 1 library ieee;  2 use ieee.std_logic_1164.all;  3 4 entity test is  5  port(  6  rst : in std_logic;  7  clk : in std_logic;  8  we : in std_logic;  9  wr_data1 : in std_logic_vector(7 downto 0);  10  wr_data2 : in std_logic_vector(7 downto 0);  11  wr_addr : in integer range 0 to 255;  12  distance : out integer range 0 to 255;  13  norm_distance:out integer range 0 to 255;  14  sum : out integer range 0 to 255;  15  vout : out std_logic;  16  no_match : out std_logic  17  );  18 end entity;  19 20 architecture rtl of test is  21 22 signal rd_data1 : std_logic_vector(7 downto 0);  23 signal rd_data2 : std_logic_vector(7 downto 0);  24 signal rd_addr1 : integer range 0 to 255 := 0;  25 signal rd_addr2 : integer range 0 to 255 := 0;  26 signal accum : integer range 0 to 255 := 0;  27 signal dis : integer range 0 to 255 := 0;  28 signal norm_dis : integer range 0 to 255 := 0;  29 signal n : integer range 0 to 255 := 0;  30 signal n_of_samples : integer range 0 to 255 := 0;  31 type states is (s0,s1,s2);  32 signal state: states;  33 34 component wr_rd_ram  35  port(  36  clk : in std_logic;  37  we : in std_logic;  38  wr_data : in std_logic_vector(7 downto 0);  39  wr_addr : in integer range 0 to 255;  40  rd_addr : in integer range 0 to 255;  41  rd_data : out std_logic_vector(7 downto 0)  42  );  43 end component;  44 45 begin  46 47 ram1:entity work.wr_rd_ram  48  port map(  49  clk => clk,  50  we => we,  51  wr_data => wr_data1,  52  wr_addr => wr_addr,  53  rd_addr => rd_addr1,  54  rd_data => rd_data1  55  );  56 57 ram2:entity work.wr_rd_ram  58  port map(  59  clk => clk,  60  we => we,  61  wr_data => wr_data2,  62  wr_addr => wr_addr,  63  rd_addr => rd_addr2,  64  rd_data => rd_data2  65  );  66 process(rst,clk)  67 begin  68 if rst = '1' then  69 70  rd_addr1 <= 0;  71  rd_addr2 <= 0;  72  accum <= 0;  73  N <= 0;  74  state <= s0;  75  vout <= '0';  76  no_match <= '0';  77  distance <= 0;  78 elsif rising_edge(clk) then  79 if we = '0' then  80  vout <= '0';  81  no_match <= '0';  82  state <= s2;  83  case state is  84  when s0 =>  85  rd_addr2 <= rd_addr2 + 1;  86  if rd_data2 = rd_data1 then  87  N <= N + 1 ;  88  state <= s1;  89  dis <= abs (rd_addr1 - rd_addr2);  90  accum <= accum + dis;  91  vout <= '1';  92  elsif rd_addr2 = 255 then  93  rd_addr2 <= 0;  94  state <= s2;  95  end if;  96 97  when s1 =>  98  rd_addr1 <= rd_addr1 + 1;  99   100  rd_addr2 <= 0;  101  state <= s0;  102 103  when s2 =>  104  no_match <= '1';  105  vout <= '0' ;  106  state <= s0;  107   108 109  when others => null;  110 111  end case;  112   113 end if;  114 end if;  115 distance <= dis ;  116 sum <= accum ;  117 end process;  118 process (n,accum)  119 begin  120 if (n mod 2) /= 0 then  121 N_of_samples <= (n*n)-1;  122 norm_dist <= dis / N_of_samples;  123 else  124 N_of_samples <= (n*n);  125 norm_dis <= dis / N_of_samples;  126 127 end if;  128 norm_distance <= norm_dis;  129 end process; 
also it gave me error divide by zero

: Edited by Moderator

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basma wrote:
> if rst = '1' then
>    N     <= 0;
> ...
> if (n mod 2) /= 0 then
>    ...
> else
>    N_of_samples <= (n*n);
>    norm_dis <= dis / N_of_samples;
> end if;
>
> also it gave me error divide by zero
Just start thinking: what will happen if if reset is asserted? What is
0*0?

BTW: add the [] around  vhdl  and  /vhdl
So it looks like [/vhdl] after the end and [vhdl] before the beginning
of the VHDL code.

: Edited by Moderator

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After changing 'norm_dist' to 'norm_dis', and add a missing 'end

Did you have a testbench?

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Duke Scarring wrote:
> After changing 'norm_dist' to 'norm_dis', and add a missing 'end
>
> Did you have a testbench?

sorry for missing it ,but also if i did it gave me error divid by zero

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> Just start thinking: what will happen if if reset is asserted? What is
> 0*0?
all i want i have a counter count the number of input sample i want to
fatch the result from this counter to test it ,because it gave me
values(0,1,2....100)i want to test if 100 is even oe odd and divide
distance on it. but how i can make it

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