Forum: FPGA, VHDL & Verilog Verilog module

von Need help designing a circuit (Guest)

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Define and design a circuit which receives a one-bit wave form and shows 
on its three one-bit outputs, by one clock cycle long positive impulses, 
the following events:
-any positive transition of the input signal
-any negative transition of the input signal
-any transition of the input signal

von Bitflüsterer (Guest)

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No. Do your homework yourself.

Please post specific questions. We suppose that you followed lessons 
carefully, made notes, performed any exercises and read at least one 
book about verilog and digital design. We also suppose that you are 
familiar with digital basics.

von Need help designing a circuit (Guest)

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I'm not. That is why I am asking for help. I'm not here to be judged, I 
am here to learn and understand. I seek help on the internet, because I 
couldn't turn anywhere else. But this is not the issue and if you want 
to help me, fine, if not don't be judgemental, just don't reply.

von Bitflüsterer (Guest)

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OK. You asked me (if not specific but as a member of an open group).
You furthermore, impolitely just cited your assignment. But however: I 
don't jugde but tell the clear policy here: We don't do any homework for 
others. You may, as I said, pose specific questions which clearly show 
that you stressed your brain before and with a reasonable backround. 
Otherwise don't argue but leave.

von Bitflüsterer (Guest)

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Let me give you a hint on what I mean:

Your assignment contains expressions like "a positive transition", "a 
negative transition" and "any transition".

These are basic matters in digital design and the verilog language as 

You may:

a) not know how to express these "things" in verilog. -> I suppose that 
you either noted syntax and meaning of that things during lessons or 
read it in a book (or any paper your teacher gave out). In such case, 
read it just again. If you still don't understand that, cite the 
questionable sentence(s) and explain what detail isn't understood by you 
or seems to impose contradictions to any of your other assumptions about 
the matter.

b) actually not know how to "combine it" (form a proper sequence) 
syntactically with other verilog expressions in a way which makes them a 
precondition for the desired ouput. -> This is in essence the same case 
as a, but you may face unforeseen, unconsidered implications in this 
very case which worry you. -> Then it would be appropriate to show us 
your attempt and your difficulties (i.e. error messages).

Hope that explanation helps to clarify the issue.


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Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.