Hi..... I used signal(0 to 64800)integer in VHDL and which is not synthesizing.... Insted of using signal/variable is there any method we can use for large values.... ? Ex: Buf1(64799 downto 0);--integers Buf1(64799 downto 0);
I can't see any problem with the declaration shown. Please post complete and minimal code which shows the problem along with the error message(s). In case of VHDL this consists an entity and an appropriate testbench.
Here I used temp0 as signal which is not synthesizing....Which code as shown below help me out in this issue.... modelsim 6.5 working fine but for xilinx 10.3 which is not synthesing.....
1 | library ieee ; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.numeric_std.all; |
4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
5 | use ieee.numeric_std.signed; |
6 | |
7 | entity parity_int is |
8 | port( clk : in std_logic; |
9 | reset: in std_logic; |
10 | nm_sh_sel:in std_logic; |
11 | code_rate:in std_logic_vector(3 downto 0); |
12 | K_ldpc: in std_logic_vector(15 downto 0); |
13 | N_ldpc:in std_logic_vector(15 downto 0); |
14 | input1: in std_logic; |
15 | output1: out std_logic); |
16 | |
17 | end parity_int; |
18 | |
19 | architecture arch of parity_int is |
20 | --Both normal and short are in one array. if we select normal then it gives 0 to 9 and
|
21 | -- if we select the short then code_rate plus 6 need to add.
|
22 | type Q_ldpc_normal is array (0 to 14) of integer; |
23 | constant Q_ldpc:Q_ldpc_normal:=(90,72,60,45,36,30,36,30,27,25,18,15,12,10,8); |
24 | |
25 | signal count1:integer; |
26 | signal s:integer; |
27 | signal t:integer; |
28 | signal temp0:std_logic_vector(0 to 64799); |
29 | signal cd_rate:std_logic_vector(3 downto 0); |
30 | |
31 | begin
|
32 | cd_rate <= code_rate when nm_sh_sel = '0' else code_rate + 6 ; |
33 | |
34 | process(clk,reset) |
35 | begin
|
36 | if((clk'event and clk = '1') or reset = '1') then |
37 | if reset = '1' then |
38 | count1 <= 0; |
39 | else
|
40 | if count1 = to_integer(unsigned(N_ldpc))+to_integer(unsigned(K_ldpc)) + 1 then --32400+64800 |
41 | count1 <= 0; |
42 | else
|
43 | count1 <= count1 + 1; |
44 | end if; |
45 | end if; |
46 | end if; |
47 | end process; |
48 | |
49 | process(count1,t) |
50 | begin
|
51 | |
52 | if reset = '1' then |
53 | s <= 0; |
54 | else
|
55 | |
56 | if count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1<to_integer(unsigned(N_ldpc)) +1 then |
57 | |
58 | if s = 360 then |
59 | s <= 0; |
60 | |
61 | else
|
62 | |
63 | s <= s + 1; |
64 | |
65 | end if; |
66 | end if; |
67 | end if; |
68 | end process; |
69 | |
70 | process(count1) |
71 | begin
|
72 | |
73 | if reset = '1' then |
74 | t <= 0; |
75 | else
|
76 | if count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1 < to_integer(unsigned(N_ldpc)) + 1 then |
77 | if t = Q_ldpc(to_integer(unsigned(cd_rate))) then |
78 | t <= 0; |
79 | |
80 | else
|
81 | |
82 | if s = 360 then |
83 | t <= t + 1; |
84 | end if; |
85 | end if; |
86 | end if; |
87 | end if; |
88 | end process; |
89 | |
90 | process(count1,reset) |
91 | begin
|
92 | if count1 >= 1 and count1 < to_integer(unsigned(K_ldpc)) + 1 then |
93 | temp0(count1 - 1) <= input1; -- it took one extra cycle because input delay by one cycle... |
94 | |
95 | elsif count1 >= to_integer(unsigned(K_ldpc)) + 1 and count1 < to_integer(unsigned(N_ldpc)) + 1 and t < 90 then |
96 | temp0(to_integer(unsigned(K_ldpc)) + (360 * t) + s ) <= input1; |
97 | output1 <= temp0(count1 - to_integer(unsigned(K_ldpc)) - 1);----32401-32400-1=0 |
98 | |
99 | elsif count1 >= to_integer(unsigned(N_ldpc)) + 1 and count1 < (to_integer(unsigned(N_ldpc)) + to_integer(unsigned(K_ldpc)) + 1) then |
100 | output1 <= temp0(count1 - to_integer(unsigned(K_ldpc)) - 1); |
101 | |
102 | end if; |
103 | |
104 | end process; |
105 | end arch; |
:
Edited by Moderator
The file extension for VHDL files is "vhd". Please use tags as mentioned in the "formatting" section. It is most likely that you got some warnings and errors. At least because:
1 | signal temp0:std_logic_vector(0 to 64799); |
does not declare an integer in the range from 0 to 64799 but a standard logic vector (i.e. a bit vector) with indixes 0 to 64799 instead which is far to large, to broad, to be synthesized.
I'm sorry: It must be: "... which is far too large, too broad, to be synthesized."
Vinayak S. wrote: > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > use ieee.numeric_std.signed; You really don't know what you are doing? Just digging around? Take these two:
1 | use ieee.std_logic_1164.all; |
2 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
Or those:
1 | use ieee.std_logic_1164.all; |
2 | use ieee.numeric_std.signed; |
Or (much better) this one:
1 | use ieee.numeric_std.all; |
But never ever use all of them together!! This forms a combinatorial loop:
1 | process(count1,t) |
2 | begin
|
3 | |
4 | if reset = '1' then |
5 | s <= 0; |
6 | else
|
7 | :
|
8 | s <= s + 1; |
You just don't see it in simulation because the sensitivity list is incomplete: s is missing... :-/ Same for t in the following:
1 | process(count1) |
2 | begin
|
3 | |
4 | if reset = '1' then |
5 | t <= 0; |
6 | else
|
7 | :
|
8 | t <= t + 1; |
And what the heck is this:
1 | process(clk,reset) |
2 | begin
|
3 | if((clk'event and clk = '1') or reset = '1') then |
4 | if reset = '1' then |
5 | count1 <= 0; |
6 | else
|
7 | if count1 = |
8 | count1 <= 0; |
9 | else
|
10 | count1 <= count1 + 1; |
A kind of asynchronous reset hidden in the clocked part of a process? Where did you find this way of VHDL coding? Vinayak S. wrote: > modelsim 6.5 working fine but ... ... your simulation is wrong because of the mostly incomplete sensitivity lists.
:
Edited by Moderator
No worth in mentioning all the other ... hmm ... peculiarities. An attempt to write a DVB-T decoder (http://embdev.net/topic/322606#3509435) which on the other hand does not know basic datatypes... Waste of time.
Thank you for valuable reply....
1 | process(clk,reset) ---- counter |
2 | begin
|
3 | if reset='1' then |
4 | count1 <= 0; |
5 | |
6 | elsif rising_edge(clk) then |
7 | count1 <= 0; |
8 | |
9 | if count1 =64800 then |
10 | count1 <= 0; |
11 | else
|
12 | count1 <= count1 + 1; |
13 | end if; |
14 | end if; |
15 | end process; |
I modified counter program like that "THIS WAY IS GOOD"....?
:
Edited by Moderator
Vinayak S. wrote: > I modified counter program like that "THIS WAY IS GOOD"....? Yes, because thats the usual way to describe a counter. Apart from the asynchronous reset and the fact that one line isn't necessary:
1 | :
|
2 | elsif rising_edge(clk) then |
3 | count1 <= 0; -- not useful and not necessary |
4 | if count1 =64800 then |
5 | count1 <= 0; |
6 | else
|
7 | :
|
Thank you for correcting...... I stack in designing pls help me..... What is the solution for large values like 64800*8 interger values need to store in register/buffer before using this reg/buf. Means to say I have store large values of Address and utilize them in program.
@Vinayak S. (vinayak_s) >I stack in designing pls help me..... No, you are lacking basic knowledge of VHDL and digital design. VHDL ist NOT just another programming language! It is, as the name implies, a hardware description language. >What is the solution for large values like 64800*8 interger values need >to store in register/buffer before using this reg/buf. A RAM. Available in any decent FPGA. >Means to say I have store large values of Address and utilize them in >program. Just do it. After you did your homework and got a grip of the basics. Otherwise, forget it.
What do you want? An integer which can store values in the range from 0 to x ? or do you want to have a signal that contains x bits? e.g. integer range 0 to 1023 will "produce" a 10bit wide Signal which can contain values from 0 to 1023 std_logic_vector(1023 downto 0) will "produce" a 1024bit wide signal which can contain 2^1024 different binary values (0 to something very very large)
Vinayak S. wrote: > Its about 64800*16-bit 1.3 MBits embedded memory nowadays is in every upper range FPGA. WHICH one do you use? > and I need it for 8 signals/array in VHDL.... WHAT is your actual problem? WHAT task do you have to solve? Vinayak S. wrote: > I stack in designing pls help me..... HOW could anyone help you? You don't answer any question, instead you only repeat useless facts like a mantra...
Vinayak S. wrote: > I require memory of 64800*16*8=7Mbits...... so you will have to connect it externally. And of course you cannot implement that simply with one line of code in your VHDL description. Instead you must implement a RAM controller to access the external memory. But: maybe you simply overestimate your secret problem... > I require memory of 64800*16*8=7Mbits...... For what? Where does the data come from? Where does it go to? In what way must the data be manipulated? What data rates do you need on the whole system? 5 questions waiting for at least 5 answers.
I`m designing interleaver which does`t have input output formule. Means if first bit comes it should be place in 100th positon like that or output first bit at 100th place... In a system like that 64800 bits need to interleave before sending. previously I store it in signal but which not synthesize so i think for RAM/ROM... here also got memory problem there are 8 different interleaving methods. Means 64K into 8 different file(to store data).
Hi, What the heck should this be? and why you need 8x64k for that, if its a temporary buffer you'll need it just once. And why do you need a FPGA for that?
Vinayak S. wrote: > Its a part of project of DVB-T2. I have to save all values no option. DVB-T2 ist the most komplex existing TV broadcast standard. Trying to implement it on a Spartan3A is akin trying to build a Formula I racing car using a Tata chassis. Vinayak S. wrote: > I`m using "Spartan 3A DSP". > > I require memory of 64800*16*8=7Mbits...... The largest Spartan3A DSP has only about 2Mbit block ram.
Hello, just looked at the dvb-t2 standart, are you implementing a FECFRAME Bit-Interleaver?
Yes, I`m implimenting a "Bit Interleaver"... I also refereeing same PDF only... I also implemented Interleaver but which not synthesizing for large buffer I used and I asked solution for many: what they told is go with RAM/ROM implementation but now facing problem of momory.. for differnt Nldpc or Qldpc, values to be interleav is change. so only I`m asking is there any other way of implementation or how effectively use RAM/ROM.... pls refer figure attached........
:
Edited by User
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