Salut tout le monde , j`'ai un problème avec mon code. Mon but est d,obtenir une horloge de période 2s. voila mon code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity clk_enabler is Port ( clk_100Mhz : in STD_LOGIC; new_clk : out STD_LOGIC); end clk_enabler; architecture clockenabler of clk_enabler is signal prescaler : std_logic_vector(25 downto 0); signal clk_2s : std_logic; begin gen_clk : process (clk_100Mhz) begin -- process gen_clk clk_2s <= '0'; prescaler <= (others => '0'); if rising_edge(clk_100Mhz) then -- rising clock edge if prescaler = X"BEBC200" then -- 200000000 in hex prescaler <= (others => '0'); clk_2s <= not clk_2s; else prescaler <= STD_LOGIC_VECTOR(unsigned(prescaler) + "1") ; end if; end if; end process; new_clk <= clk_2s ; end; L'erreur est la suivante : Signal prescaler cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release. S'il vous plait j'ai besoin d'aide

Bilel wrote: > S'il vous plait j'ai besoin d'aide Simply kick out this two lines:

1 | clk_2s <= '0'; |

2 | prescaler <= (others => '0'); |

But this is not the way to make a clock inside a FPGA!

Thanks but what do you mean kick them out? retrieve them? And this doesn't give me a clock with 0.5 htz frequency? how do i do it? thanks

I wrote this entity Clk_enabler is Port ( clk100M : in STD_LOGIC; clk : out STD_LOGIC); end Clk_enabler; architecture Behavioral of Clk_enabler is signal counter : integer:=0; begin process(clk100M) begin if rising_edge(clk100M) then if (counter = 200000000) then counter<=0; else counter <= counter + 1; end if; end if; end process; process(counter) begin if (counter = 200000000) then clk<='1'; else clk<='0'; end if; end process; end Behavioral; but it didn't work there was an error n 200000000

Bilel Ben Jabeur wrote: > I wrote this Pls embed your VHDL code in the following tokens (without spaces): [ vhdl ] your code [ /vhdl ] And use tabs and spaces to indent your code! > I wrote this > entity Every VHDL description starts well before the keyword "entity"! > but it didn't work there was an error n 200000000 And how does this error look like? Whats the error message EXACTLY? Try that:

1 | library IEEE; |

2 | use IEEE.STD_LOGIC_1164.ALL; |

3 | use IEEE.NUMERIC_STD.ALL; |

4 | |

5 | entity Clk_enabler is |

6 | Port ( clk100M : in STD_LOGIC; |

7 | clk : out STD_LOGIC); |

8 | end Clk_enabler; |

9 | |

10 | architecture Behavioral of Clk_enabler is |

11 | signal counter : integer RANGE 0 TO 200000000 := 0; |

12 | ```
begin
``` |

13 | |

14 | process (clk100M) begin |

15 | if rising_edge(clk100M) then |

16 | if (counter = 200000000) then |

17 | counter<=0; |

18 | clk<='1'; |

19 | ```
else
``` |

20 | counter <= counter + 1; |

21 | clk<='0'; |

22 | end if; |

23 | end process; |

24 | end Behavioral; |

BTW: clk MUST NOT be used as a clock! It is only an enable signal!

Thanks a lot. You've been really helpfull. In my project, I need to use CLK in another source(VHDL module) :

1 | |

2 | if rising_edge(clk)... |

Can I? (by the way I'm new at this) How do I connect the 2 vhdl modules so that the (clk) output of the first one (the one you've been helping me with)can be an input for the second one? do I have to create another module? Thanks again.

Have a look at clock enables. That's the way you should do it. You shouldn't use gated clocks, that's what Lothar was talking about.

Bilel Ben Jabeur wrote: > Can I? (by the way I'm new at this) Lothar Miller wrote: > clk MUST NOT be used as a clock! It is only an enable signal! So use it that way!

1 | library IEEE; |

2 | use IEEE.STD_LOGIC_1164.ALL; |

3 | use IEEE.NUMERIC_STD.ALL; |

4 | |

5 | entity Clk_enabler is |

6 | Port ( clk100M : in STD_LOGIC; |

7 | clk : out STD_LOGIC); |

8 | end Clk_enabler; |

9 | |

10 | architecture Behavioral of Clk_enabler is |

11 | signal counter : integer RANGE 0 TO 200000000 := 0; |

12 | signal twoseconds : std_logic := '0'; |

13 | ```
begin
``` |

14 | |

15 | process (clk100M) begin |

16 | if rising_edge(clk100M) then |

17 | if (counter = 200000000) then |

18 | counter<=0; |

19 | twoseconds <='1'; |

20 | ```
else
``` |

21 | counter <= counter + 1; |

22 | twoseconds <='0'; |

23 | end if; |

24 | end process; |

25 | end Behavioral; |

26 | |

27 | |

28 | process (clk100M) begin |

29 | if rising_edge(clk100M) then -- the one and only clock in the design!!!! |

30 | if (twoseconds ='1') then -- this is a clock enable |

31 | ```
...
``` |

:
Edited by Moderator

I really am new at this. My project is a system fot street lights. First step : divide the clock in the first vhdl module, as Lothar said :

1 | library IEEE; |

2 | use IEEE.STD_LOGIC_1164.ALL; |

3 | use IEEE.NUMERIC_STD.ALL; |

4 | |

5 | entity Clk_enabler is |

6 | Port ( clk100M : in STD_LOGIC; |

7 | clk : out STD_LOGIC); |

8 | end Clk_enabler; |

9 | |

10 | architecture Behavioral of Clk_enabler is |

11 | signal counter : integer RANGE 0 TO 200000000 := 0; |

12 | ```
begin
``` |

13 | |

14 | process (clk100M) begin |

15 | if rising_edge(clk100M) then |

16 | if (counter = 200000000) then |

17 | counter<=0; |

18 | clk<='1'; |

19 | ```
else
``` |

20 | counter <= counter + 1; |

21 | clk<='0'; |

22 | end if; |

23 | end process; |

24 | end Behavioral; |

Second step is my state machine in the second module. Here it is

1 | library IEEE; |

2 | use IEEE.STD_LOGIC_1164.ALL; |

3 | ```
-- Uncomment the following library declaration if using
``` |

4 | ```
-- arithmetic functions with Signed or Unsigned values
``` |

5 | ```
--use IEEE.NUMERIC_STD.ALL;
``` |

6 | entity main is |

7 | Port ( BI : in STD_LOGIC; |

8 | ABP : in STD_LOGIC; |

9 | clk : in STD_LOGIC; |

10 | SA : out STD_LOGIC; |

11 | FPTP : out STD_LOGIC; |

12 | FPV : out STD_LOGIC; |

13 | FPO : out STD_LOGIC; |

14 | FPR : out STD_LOGIC; |

15 | FSV : out STD_LOGIC; |

16 | FSO : out STD_LOGIC; |

17 | FSR : out STD_LOGIC); |

18 | end main; |

19 | architecture Behavioral of main is |

20 | signal counter: NUMERIC_STD; |

21 | signal FPV1 : STD_LOGIC; |

22 | signal FPO1 : STD_LOGIC; |

23 | signal FPR1 : STD_LOGIC; |

24 | signal FSV1 : STD_LOGIC; |

25 | signal FSO1 : STD_LOGIC; |

26 | signal FSR1 : STD_LOGIC; |

27 | signal SA1 : STD_LOGIC; |

28 | signal FPTP1 : STD_LOGIC; |

29 | ```
begin
``` |

30 | process(clk, BI) |

31 | ```
begin
``` |

32 | if rising_edge(clk) then |

33 | if (BI='1') then |

34 | counter <= 0 ; |

35 | elsif (counter >=0 and counter<9) or (counter = 10) then |

36 | counter <= counter +1 ; |

37 | end if; |

38 | end if; |

39 | end process; |

40 | process(BAP) |

41 | ```
begin
``` |

42 | if (BAP='1') then |

43 | SA1 <= '1' ; |

44 | end if; |

45 | end process; |

46 | SA <= SA1; |

47 | process(SA1) |

48 | ```
begin
``` |

49 | if counter=9 then |

50 | if SA1=('1')then |

51 | FPTP1 <= '1'; |

52 | SA1 <= '0' ; |

53 | counter <= counter+1 ; |

54 | else counter <= 0 ; |

55 | end if; |

56 | end if; |

57 | end process; |

58 | SA <= SA1; |

59 | FPTP <= FPTP1 ; |

60 | |

61 | ```
process
``` |

62 | ```
begin
``` |

63 | if (counter=11) then |

64 | FPTP1 <= '0'; |

65 | counter <= 0; |

66 | end if; |

67 | end process; |

68 | FPTP <= FPTP1 ; |

69 | ```
process
``` |

70 | ```
begin
``` |

71 | if (counter=0) then |

72 | FPV1 <= '1' ; |

73 | FPO1 <= '0' ; |

74 | FPR1 <= '0' ; |

75 | FSV1 <= '0' ; |

76 | FSO1 <= '0' ; |

77 | FSR1 <= '1' ; |

78 | elsif (counter=4) then |

79 | FPV1 <= '0' ; |

80 | FPO1 <= '1' ; |

81 | FPR1 <= '0' ; |

82 | FSV1 <= '0' ; |

83 | FSO1 <= '0' ; |

84 | FSR1 <= '1' ; |

85 | elsif (counter=5) then |

86 | FPV1 <= '0' ; |

87 | FPO1 <= '0' ; |

88 | FPR1 <= '1' ; |

89 | FSV1 <= '1' ; |

90 | FSO1 <= '0' ; |

91 | FSR1 <= '0' ; |

92 | elsif (counter=8) then |

93 | FPV1 <= '0' ; |

94 | FPO1 <= '0' ; |

95 | FPR1 <= '1' ; |

96 | FSV1 <= '0' ; |

97 | FSO1 <= '1' ; |

98 | FSR1 <= '0' ; |

99 | end if; |

100 | end process; |

101 | |

102 | FPV <= FPV1 ; |

103 | FPO <= FPO1 ; |

104 | FPR <= FPR1 ; |

105 | FSV <= FSV1 ; |

106 | FSO <= FSO1 ; |

107 | FSR <= FSR1 ; |

108 | |

109 | |

110 | end Behavioral; |

What do I do so that (clk) the input of the second module is the output of the first?

This is a combinatorial loop (aka. combinational loop):

1 | process(SA1) |

2 | ```
begin
``` |

3 | if counter=9 then |

4 | if SA1=('1')then |

5 | FPTP1 <= '1'; |

6 | SA1 <= '0' ; |

7 | counter <= counter+1 ; |

In real life "counter" here is just a very high frequency noise generator. It will not do any useful things... Simulation will look ok, because of the missing signal counter in the sensitivity list. And this here is not synthesizeable at all:

1 | ```
process
``` |

2 | ```
begin
``` |

3 | if (counter=0) then |

A process with no sensitivity list needs a "wait" statement somewhere inside. And of course: you cannot drive "counter" in more than one process.

:
Edited by Moderator

Lothar Miller wrote: > This is a combinatorial loop (aka. combinational > loop):process(SA1) > begin > if counter=9 then > if SA1=('1')then > FPTP1 <= '1'; > SA1 <= '0' ; > counter <= counter+1 ; > In real life "counter" here is just a very high frequency noise > generator. It will not do any useful things... > Simulation will look ok, because of the missing signal counter in the > sensitivity list. Could you please explain why this is a combinatorial loop? Or why "counter" would be incremented all the time? I can see the problems in the posted vhdl code, but can't see the loop in this particular process....

guest (not op) wrote: > I can see the problems in the posted vhdl code, but can't see the loop > in this particular process.... There is a counter without a clock. That's a combinatorial loop. In the case here it is hidden behind a incomplete sensitivity list and a littlte bit logic, and so it cannot easily seen in simulation. And also maybe the synthesizer cannot recognize it... :-( > Or why "counter" would be incremented all the time? In fact its far more complicated here, because the enable logic for the counter itself uses the counter. That can lead to very unexpected and strange behaviour... So indeed "counter" will not increment all the time. I missed the "if counter=9". Bilel Ben Jabeur wrote: > so a signal can't be be in two sensitivity lists of different processes A signal must be in a process sensitivity list if it makes the recalculation of that process necessary. So of course a signal can be in lots of sensitivity lists. But only one process or one concurrent statement can assign a value to a signal. BTW always keep in mind: the sensitivity list is ONLY for the simulator, it isn't used by the synthesizer at all!

:
Edited by Moderator