EmbDev.net

Forum: FPGA, VHDL & Verilog solution for large memory requirement for FPGA


von Vinayak S. (vinayak_s)


Rate this post
useful
not useful
Hello,
I am designing "time interleaver" for DVB-T2, which is require large 
memory to be store before interleave.
Means, 32400 values in a one row and like that 1024 column of data need 
to be store before doing operation.

32400 rows, 1024 columns and each location of 17-bits wide.

32400  1024  17-bits = 564019200 bits need to be store....

What is the solution for this to be done.......?

I am using Spartan 3A-DSP........

von Duke Scarring (Guest)


Rate this post
useful
not useful
Just use external attached dynamic memory...

Duke

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.