Hello, In verilog code, I am doing the pre-synthesis simulation correctly for the attached attachment "text.txt" but when I am doing the synthesis and then checking the simulation result then it is not as per the pre-synthesis simulation result. For the reference I am attaching .v file with test bench and the snapshot of pre-synthesis and post-synthesis simulation. Please give me the solution of this.
Your test.v module contains an initial statement. This statement is not part of the synthesizable subset of verilog. Check the usage guide of your synthesizer!
Thanks for the reply.. But I have used the "readmemb" which is synthesizable and I have verified it with my other code and at there it works nice..
No $readmemb is not synthesizable. Some synthesizer (i.e. Synplfy Pro) allows it usage to read memory initial value from a file during synthesis. Also your initial statement contains 2 more statements which don't fall under this exception.
So what can I do? in my other code, similar way I have done and at that time there is not problem..Here I am attaching that file's snapshot..
Nisarg Shah wrote: > So what can I do? > in my other code, similar way I have done and at that time there is not > problem..Here I am attaching that file's snapshot.. I see there lot of xxxx values, there is definitly a problem!
in the last snapshot "ipfromcompensator" the value matched because the code is written such a way that it will calculate at pos edge of clk..and it does in post-synthesis also..
Get rid of the undefineds. Example from Synplify Pro guide for assigning initial values.
1 | module top(a, b, c, clk); |
2 | input clk; |
3 | input [3:0]a, b; |
4 | output [3:0]c; |
5 | reg [3:0]c =3'b1100; |
6 | |
7 | always@(posedge clk) |
8 | begin |
9 | c<= a & b; |
10 | end |
11 | endmodule |
didn't get this..can you elaborate because output is first taken and then again "and" operation with input which is not initialized..
This is a damn sample, don't overinterpret it! The only important part is reg [3:0]c =3'b1100; (Contains a typo, should be 4'b1100, thanks Synposys)
same output after doing initializing with "reg variable=0" in place of "initial readmemb"
Nisarg Shah wrote: > same output after doing initializing with "reg variable=0" in place of > "initial readmemb" I am not a mond reader, how dose the code look now?
this is how it looks like after your suggestion..
Ok, How does the output look now? what about "ed"?
the "ed" is xxxx as shown in attached file
This
1 | output reg [9:0] c1 =0; |
for example isn't the exact same syntax as the Synplify sample, which would be.
1 | output [9:0] c1; |
2 | .... |
3 | reg [9:0] c1 =0; |
(IMO should your version work too, but i have not testet it= In your trace it looks like it didn't work at all. 1) Are your sure that you have rerun the synthesiser? 2) What is your synthesyser and version. 3) What dose the your synthesysers guide say about assigning initial values?
yes i have rerun the synthesizer.. version is symplify pro E-2010.09A-1 initialization can be valid both, what ever you say as well as readmemb.
same result after declaring like output [5:0] b ; output [5:0] q ; output reg [5:0] ed; output [6:0] c ; output [9:0] c1 ; reg [5:0] q = 0; reg [5:0] b = 0 ; reg [6:0] c =0 ; reg [9:0] c1 =0;
Nisarg Shah wrote: > yes i have rerun the synthesizer.. > version is symplify pro E-2010.09A-1 > initialization can be valid both, what ever you say as well as readmemb. But not this:
1 | $readmemb("init.dat", marray); |
2 | b = marray[0]; |
In your traces you can see that initialization does not work at all. But the reason may be your simulator (and not the synthesiser). On Lattice FPGAs i would probably need to instantiate the GSR component in the test bench to simulate the correct behaviour. Also you need to make sure your FPGA (which one) support initial values on registers during configuration. If initial values are not possible, you need to add a reset to your deisgn.
if I remove "c1=c1+1" line from the code then the output is as in attached file. infact c1 variable I have attached to check that initialization is done or not. and it does..but then process is not done..
and by the way as you suggest that if initial value is not supported then reset is to be added .so how can I add reset to design ? i.e reset is signal and we need to assign value so how can it be correlated?
Nisarg Shah wrote: > if I remove "c1=c1+1" line from the code then the output is as in > attached file. infact c1 variable I have attached to check that > initialization is done or not. and it does..but then process is not > done.. No, without c1=c1+1 c1 is a constant value, and optimised as such by the synthesizer. in other words it is post synthssis no longer a register.
ok..so this is optimised value shown for c1 as it is constant, isn't it??
Nisarg Shah wrote: > ok..so this is optimised value shown for c1 as it is constant, isn't > it?? Yes. Check your FPGA (which one would these be?) data sheet how registers get their initial values. If this does not help, you need to add a reset in the standard verilog way {code] always @(posedge clock) begin if( reset ) c1 <= 0; else c1 <= c1 + 1 end [/code] or asynchron (DANGER) {code] always @(posedge clock or posedge reset) begin if( reset ) c1 <= 0; else c1 <= c1 + 1 end [/code] But first check if and how your fpga supports initial values, which would the preferred way (unless you need a reset for other reasons)
I am using ACTEL (Microsemi)'s 54SXA family's A54SX32A FPGA..So can you say that whether it supports initial value or not as I have referred the datasheet but couldn't find it out..
Nisarg Shah wrote: > I am using ACTEL (Microsemi)'s 54SXA family's A54SX32A FPGA..So can you > say that whether it supports initial value or not as I have referred the > datasheet but couldn't find it out.. Can't find it either, sorry. Ask the Microsemi support or give up and add a reset to your design. Maybe the HDL-Analysist from Synplify Pro can give you a hint (technology view). Use a init value other than 0 on c1 to see if you can find it in the synthesys result.
Nisarg Shah wrote: > I am using ACTEL (Microsemi)'s 54SXA family's A54SX32A FPGA..So can you No initial values supported for these devices. But that will Synplify certainly report as warning. Have you read the tool reports???
when I used initial value of c1 = 2 and not doing any operation on it, it shows that initial value but if I do any operation on it, then it shows xxxx value..
Nisarg Shah wrote: > when I used initial value of c1 = 2 and not doing any operation on it, > it shows that initial value but if I do any operation on it, then it > shows xxxx value.. That shows the Synthesiser supports initial values but the hardware dosn't. You need to add a reset. (There should be a warning, see Ottmar posting)
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