# Forum: FPGA, VHDL & Verilog query on verilog code

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hello,

i have a doubt in verilog code..

1)for a given 32 bit input if any one input is also x then return 1 or
else return 0 using functions how do i write a code for this in verilog?

2) for a give 8 bit input if it is divisible by 4 then return 1 else 0..
donot use any arithmetic operators, loop statements ,case statements how
do i do this using functions in verilog

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Homework? Which school?

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This is just stupid homework. Generations of students figured it out
themself. The invoked process is called "learning"...

> 2) for a give 8 bit input if it is divisible by 4 then return 1 else 0..
> donot use any arithmetic operators, loop statements ,case statements
So far so good.
> how do i do this using functions in verilog
This is no special problem with verilog. How would you do it in (e.g.)
C?

I would do it this way:
Write down binary numbers and look for a pattern.
Which one is devideable by 4?
000000000 * this one
000000001
000000010
000000011
000000100 * this one
000000101
000000110
000000111
000001000 * this one
000001001
000001010
000001011
000001100 * this one
000001101
000001110
000001111
000010000 * this one
000010001
000010010
000010011
000010100 * this one
: and so on
111111000 * this one
111111001
111111010
111111011
111111100 * this one
111111101
111111110
111111111

Do you see the pattern?

Just a hint: if the lowest 2 bits are '0' the number is divideable by 4.

>  1)for a given 32 bit input if any one input is also x then return 1 or
> else return 0 using functions how do i write a code for this in verilog?
I'm a VHDL guy, but i would use a loop over the 32 bits and compare each
of them with 'x'. If one matches, i would terminate the loop an return
1.

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The following is the code..everything is fine but the final value is not
loaded into the stc..am attaching the simulation screenshots
 timescale 1ns / 1ps module testy; // Inputs reg [15:0] a; reg reset; reg clk; reg ah; reg high; reg enable; // inouts wire [3:0] bts; //outputs wire [31:0] stc; // Instantiate the Unit Under Test (UUT) pract uut0 ( .a(a), .reset(reset), .clk(clk), .ah(ah), .high(high), .enable(enable), .bts(bts) ); initial begin clk =1; high =1; ah =1; end always begin #10 clk=~clk; end always begin #20 high=~high; end always begin #40 ah =~ ah; end initial begin // Initialize Inputs a = 16'hfabe; reset = 0; enable = 1; // Wait 100 ns for global reset to finish #100; reset =1; // Add stimulus here end st uut1( .bts(bts), .stc(stc) ); endmodule 

: Edited by Moderator

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Arjun S. wrote:
> The following is the code..
Why the heck did you hijack a 3 year old thread with a completely
different topic?

> but the final value is not loaded into the stc..
Why should it? I cannot see any assignment to stc.`

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