query on verilog code

pushpalatha G. OP (Company: Spanwave) #2307282
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hello,

         i have a doubt in verilog code..


 1)for a given 32 bit input if any one input is also x then return 1 or 
else return 0 using functions how do i write a code for this in verilog? 
please help

2) for a give 8 bit input if it is divisible by 4 then return 1 else 0.. 
donot use any arithmetic operators, loop statements ,case statements how 
do i do this using functions in verilog
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lkmiller Guest #2308110
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This is just stupid homework. Generations of students figured it out 
themself. The invoked process is called "learning"...

> 2) for a give 8 bit input if it is divisible by 4 then return 1 else 0..
> donot use any arithmetic operators, loop statements ,case statements
So far so good.
> how do i do this using functions in verilog
This is no special problem with verilog. How would you do it in (e.g.) 
C?

I would do it this way:
Write down binary numbers and look for a pattern.
Which one is devideable by 4?
000000000 * this one
000000001
000000010
000000011
000000100 * this one
000000101
000000110
000000111
000001000 * this one
000001001
000001010
000001011
000001100 * this one
000001101
000001110
000001111
000010000 * this one
000010001
000010010
000010011
000010100 * this one
: and so on
111111000 * this one
111111001
111111010
111111011
111111100 * this one
111111101
111111110
111111111

Do you see the pattern?
No? Thats your problem.

Just a hint: if the lowest 2 bits are '0' the number is divideable by 4.

>  1)for a given 32 bit input if any one input is also x then return 1 or
> else return 0 using functions how do i write a code for this in verilog?
I'm a VHDL guy, but i would use a loop over the 32 bits and compare each 
of them with 'x'. If one matches, i would terminate the loop an return 
1.
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Arjun S. #3563883
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The following is the code..everything is fine but the final value is not 
loaded into the stc..am attaching the simulation screenshots
1
`timescale 1ns / 1ps

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module testy;

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  // Inputs

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  reg [15:0] a;

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  reg reset;

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  reg clk;

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  reg ah;

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  reg high;

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  reg enable;

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  // inouts

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  wire [3:0] bts;

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  //outputs

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   wire [31:0] stc;

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  // Instantiate the Unit Under Test (UUT)

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  pract uut0 (

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    .a(a), 

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    .reset(reset), 

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    .clk(clk), 

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    .ah(ah), 

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    .high(high), 

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    .enable(enable), 

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    .bts(bts)

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  );

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initial begin clk =1; high =1; ah =1; end

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always begin #10 clk=~clk; end

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always begin #20 high=~high; end

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always begin #40 ah =~ ah; end

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  initial begin

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    // Initialize Inputs

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    a = 16'hfabe;

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    reset = 0;    

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    enable = 1;

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    // Wait 100 ns for global reset to finish

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    #100;

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        reset =1;

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    // Add stimulus here

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  end

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      st uut1(

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    .bts(bts),

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    .stc(stc)

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    );

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endmodule
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