Hi All, if i have a vector such as (1,2,3,4....100) and i want to use only the last output 100 to make division on the last output from another vector such as (5,9,6,8.....200) i.e i want to divide 100/200 . can i make it in vhdl i don't know if my question is logic or not or how can i do it.
Basma Hassan wrote: > i have a vector such as (1,2,3,4....100) Show the definition of this "vector". In what language do you want to solve the problem? What is the actual problem?
if the first is [vhdl] signal dis : integer range 0 to 255 := 0; signal n : integer range 0 to 255 := 0; and i want to divide the last output from the two signals and what if there is a zero value in signal n
Basma Hassan wrote: > and i want to divide the last output from the two signals There is only one value in both of the two signals. So there is no whatsoever "last value". > and what if there is a zero value in signal n Then you are not allowed to perform a division, because the result will be inpredictable and invalid. Is this for simulation only or do you want to implement this division in real hardware?
Guest
#3533363
Lothar Miller wrote: > There is only one value in both of the two signals. So there is no > whatsoever "last value". the two signal will have values as (1,6,9,8,.....100) and the second signal will have values as (0,2,8,9.......,200) and i want to fetch the two last outputs from the two signal (100,200) and divide 100/200. > Is this for simulation only or do you want to implement this division in > real hardware? for both simulation and then for implementation in real hardware.
Basma Hassan wrote: > signal dis : integer range 0 to 255 := 0; > signal n : integer range 0 to 255 := 0; basma hassan wrote: > the two signal will have values as (1,6,9,8,.....100) and the second > signal will have values as (0,2,8,9.......,200) For sure each of the above declared signals n and dis will not take more than one value. However, if you have arrays of integer values:
1 | |
2 | |
3 | |
and the last value inside such an arry is accessed by its posistion:
1 | |
2 | |
3 | |
> for both simulation and then for implementation in real hardware. Good luck. A division in real hardware is not the easiest thing for a beginner. But: just start with it, then you will find out to ask the correct questions... Here is my code for a division in hardware: http://www.lothar-miller.de/s9y/archives/29-Division-in-VHDL.html Its in German, but just try the Google translator...
Guest
#3534017
thanks a lot Lothar Miller it was very helpful for me ,but if i have a counter count the number of input samples then the counter output (n) will be as (1,2,3,4....50) and i want to check if the numbers of samples is even do that (n*n) or if odd make that ((n*n)-1) and i want to divide distance which is signal dis : integer range 0 to 255 := 0; to the n numbers of the samples which is even or odd will e something like that if lsb = '1' then n_of samples<= ((n*n)-1); else n_of_samples <= n*n; end if; norm_dis <= dis / n_of_samples ; how can i write it in vhdl i hope y understand me and thanks for help.
Guest
#3567157
Lothar Miller wrote: > There is only one value in both of the two signals. So there is no > whatsoever "last value". yes you're right sorry for confusing but i am new in vhdl and the output from the counter gave me a stream values in simulation mode like (1,2.....,100) and i want to use the result from the counter to test it and make division on it. how i can save it and make it in vhdl code thanks a lot for help